/**
  ******************************************************************************
  * @file    pds_reg.h
  * @version V1.0
  * @date    2021-11-22
  * @brief   This file is the description of.IP register
  ******************************************************************************
  * @attention
  *
  * <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __PDS_REG_H__
#define __PDS_REG_H__

#include "bl616.h"

/* 0x0 : PDS_CTL */
#define PDS_CTL_OFFSET                        (0x0)
#define PDS_START_PS                          PDS_START_PS
#define PDS_START_PS_POS                      (0U)
#define PDS_START_PS_LEN                      (1U)
#define PDS_START_PS_MSK                      (((1U << PDS_START_PS_LEN) - 1) << PDS_START_PS_POS)
#define PDS_START_PS_UMSK                     (~(((1U << PDS_START_PS_LEN) - 1) << PDS_START_PS_POS))
#define PDS_CR_SLEEP_FOREVER                  PDS_CR_SLEEP_FOREVER
#define PDS_CR_SLEEP_FOREVER_POS              (1U)
#define PDS_CR_SLEEP_FOREVER_LEN              (1U)
#define PDS_CR_SLEEP_FOREVER_MSK              (((1U << PDS_CR_SLEEP_FOREVER_LEN) - 1) << PDS_CR_SLEEP_FOREVER_POS)
#define PDS_CR_SLEEP_FOREVER_UMSK             (~(((1U << PDS_CR_SLEEP_FOREVER_LEN) - 1) << PDS_CR_SLEEP_FOREVER_POS))
#define PDS_CR_XTAL_FORCE_OFF                 PDS_CR_XTAL_FORCE_OFF
#define PDS_CR_XTAL_FORCE_OFF_POS             (2U)
#define PDS_CR_XTAL_FORCE_OFF_LEN             (1U)
#define PDS_CR_XTAL_FORCE_OFF_MSK             (((1U << PDS_CR_XTAL_FORCE_OFF_LEN) - 1) << PDS_CR_XTAL_FORCE_OFF_POS)
#define PDS_CR_XTAL_FORCE_OFF_UMSK            (~(((1U << PDS_CR_XTAL_FORCE_OFF_LEN) - 1) << PDS_CR_XTAL_FORCE_OFF_POS))
#define PDS_CR_PDS_WIFI_SAVE_STATE            PDS_CR_PDS_WIFI_SAVE_STATE
#define PDS_CR_PDS_WIFI_SAVE_STATE_POS        (3U)
#define PDS_CR_PDS_WIFI_SAVE_STATE_LEN        (1U)
#define PDS_CR_PDS_WIFI_SAVE_STATE_MSK        (((1U << PDS_CR_PDS_WIFI_SAVE_STATE_LEN) - 1) << PDS_CR_PDS_WIFI_SAVE_STATE_POS)
#define PDS_CR_PDS_WIFI_SAVE_STATE_UMSK       (~(((1U << PDS_CR_PDS_WIFI_SAVE_STATE_LEN) - 1) << PDS_CR_PDS_WIFI_SAVE_STATE_POS))
#define PDS_CR_PDS_PD_LDO11                   PDS_CR_PDS_PD_LDO11
#define PDS_CR_PDS_PD_LDO11_POS               (4U)
#define PDS_CR_PDS_PD_LDO11_LEN               (1U)
#define PDS_CR_PDS_PD_LDO11_MSK               (((1U << PDS_CR_PDS_PD_LDO11_LEN) - 1) << PDS_CR_PDS_PD_LDO11_POS)
#define PDS_CR_PDS_PD_LDO11_UMSK              (~(((1U << PDS_CR_PDS_PD_LDO11_LEN) - 1) << PDS_CR_PDS_PD_LDO11_POS))
#define PDS_CR_PDS_PD_BG_SYS                  PDS_CR_PDS_PD_BG_SYS
#define PDS_CR_PDS_PD_BG_SYS_POS              (5U)
#define PDS_CR_PDS_PD_BG_SYS_LEN              (1U)
#define PDS_CR_PDS_PD_BG_SYS_MSK              (((1U << PDS_CR_PDS_PD_BG_SYS_LEN) - 1) << PDS_CR_PDS_PD_BG_SYS_POS)
#define PDS_CR_PDS_PD_BG_SYS_UMSK             (~(((1U << PDS_CR_PDS_PD_BG_SYS_LEN) - 1) << PDS_CR_PDS_PD_BG_SYS_POS))
#define PDS_CR_PDS_CTRL_GPIO_IE_PU_PD         PDS_CR_PDS_CTRL_GPIO_IE_PU_PD
#define PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_POS     (6U)
#define PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_LEN     (1U)
#define PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_MSK     (((1U << PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_LEN) - 1) << PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_POS)
#define PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_UMSK    (~(((1U << PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_LEN) - 1) << PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_POS))
#define PDS_CR_PDS_PD_DCDC18                  PDS_CR_PDS_PD_DCDC18
#define PDS_CR_PDS_PD_DCDC18_POS              (7U)
#define PDS_CR_PDS_PD_DCDC18_LEN              (1U)
#define PDS_CR_PDS_PD_DCDC18_MSK              (((1U << PDS_CR_PDS_PD_DCDC18_LEN) - 1) << PDS_CR_PDS_PD_DCDC18_POS)
#define PDS_CR_PDS_PD_DCDC18_UMSK             (~(((1U << PDS_CR_PDS_PD_DCDC18_LEN) - 1) << PDS_CR_PDS_PD_DCDC18_POS))
#define PDS_CR_PDS_GATE_CLK                   PDS_CR_PDS_GATE_CLK
#define PDS_CR_PDS_GATE_CLK_POS               (8U)
#define PDS_CR_PDS_GATE_CLK_LEN               (1U)
#define PDS_CR_PDS_GATE_CLK_MSK               (((1U << PDS_CR_PDS_GATE_CLK_LEN) - 1) << PDS_CR_PDS_GATE_CLK_POS)
#define PDS_CR_PDS_GATE_CLK_UMSK              (~(((1U << PDS_CR_PDS_GATE_CLK_LEN) - 1) << PDS_CR_PDS_GATE_CLK_POS))
#define PDS_CR_PDS_MEM_STBY                   PDS_CR_PDS_MEM_STBY
#define PDS_CR_PDS_MEM_STBY_POS               (9U)
#define PDS_CR_PDS_MEM_STBY_LEN               (1U)
#define PDS_CR_PDS_MEM_STBY_MSK               (((1U << PDS_CR_PDS_MEM_STBY_LEN) - 1) << PDS_CR_PDS_MEM_STBY_POS)
#define PDS_CR_PDS_MEM_STBY_UMSK              (~(((1U << PDS_CR_PDS_MEM_STBY_LEN) - 1) << PDS_CR_PDS_MEM_STBY_POS))
#define PDS_CR_PDS_GLB_REG_RESET_PROTECT      PDS_CR_PDS_GLB_REG_RESET_PROTECT
#define PDS_CR_PDS_GLB_REG_RESET_PROTECT_POS  (10U)
#define PDS_CR_PDS_GLB_REG_RESET_PROTECT_LEN  (1U)
#define PDS_CR_PDS_GLB_REG_RESET_PROTECT_MSK  (((1U << PDS_CR_PDS_GLB_REG_RESET_PROTECT_LEN) - 1) << PDS_CR_PDS_GLB_REG_RESET_PROTECT_POS)
#define PDS_CR_PDS_GLB_REG_RESET_PROTECT_UMSK (~(((1U << PDS_CR_PDS_GLB_REG_RESET_PROTECT_LEN) - 1) << PDS_CR_PDS_GLB_REG_RESET_PROTECT_POS))
#define PDS_CR_PDS_ISO_EN                     PDS_CR_PDS_ISO_EN
#define PDS_CR_PDS_ISO_EN_POS                 (11U)
#define PDS_CR_PDS_ISO_EN_LEN                 (1U)
#define PDS_CR_PDS_ISO_EN_MSK                 (((1U << PDS_CR_PDS_ISO_EN_LEN) - 1) << PDS_CR_PDS_ISO_EN_POS)
#define PDS_CR_PDS_ISO_EN_UMSK                (~(((1U << PDS_CR_PDS_ISO_EN_LEN) - 1) << PDS_CR_PDS_ISO_EN_POS))
#define PDS_CR_PDS_WAIT_XTAL_RDY              PDS_CR_PDS_WAIT_XTAL_RDY
#define PDS_CR_PDS_WAIT_XTAL_RDY_POS          (12U)
#define PDS_CR_PDS_WAIT_XTAL_RDY_LEN          (1U)
#define PDS_CR_PDS_WAIT_XTAL_RDY_MSK          (((1U << PDS_CR_PDS_WAIT_XTAL_RDY_LEN) - 1) << PDS_CR_PDS_WAIT_XTAL_RDY_POS)
#define PDS_CR_PDS_WAIT_XTAL_RDY_UMSK         (~(((1U << PDS_CR_PDS_WAIT_XTAL_RDY_LEN) - 1) << PDS_CR_PDS_WAIT_XTAL_RDY_POS))
#define PDS_CR_PDS_PWR_OFF                    PDS_CR_PDS_PWR_OFF
#define PDS_CR_PDS_PWR_OFF_POS                (13U)
#define PDS_CR_PDS_PWR_OFF_LEN                (1U)
#define PDS_CR_PDS_PWR_OFF_MSK                (((1U << PDS_CR_PDS_PWR_OFF_LEN) - 1) << PDS_CR_PDS_PWR_OFF_POS)
#define PDS_CR_PDS_PWR_OFF_UMSK               (~(((1U << PDS_CR_PDS_PWR_OFF_LEN) - 1) << PDS_CR_PDS_PWR_OFF_POS))
#define PDS_CR_PDS_PD_XTAL                    PDS_CR_PDS_PD_XTAL
#define PDS_CR_PDS_PD_XTAL_POS                (14U)
#define PDS_CR_PDS_PD_XTAL_LEN                (1U)
#define PDS_CR_PDS_PD_XTAL_MSK                (((1U << PDS_CR_PDS_PD_XTAL_LEN) - 1) << PDS_CR_PDS_PD_XTAL_POS)
#define PDS_CR_PDS_PD_XTAL_UMSK               (~(((1U << PDS_CR_PDS_PD_XTAL_LEN) - 1) << PDS_CR_PDS_PD_XTAL_POS))
#define PDS_CR_PDS_CTRL_SOC_ENB               PDS_CR_PDS_CTRL_SOC_ENB
#define PDS_CR_PDS_CTRL_SOC_ENB_POS           (15U)
#define PDS_CR_PDS_CTRL_SOC_ENB_LEN           (1U)
#define PDS_CR_PDS_CTRL_SOC_ENB_MSK           (((1U << PDS_CR_PDS_CTRL_SOC_ENB_LEN) - 1) << PDS_CR_PDS_CTRL_SOC_ENB_POS)
#define PDS_CR_PDS_CTRL_SOC_ENB_UMSK          (~(((1U << PDS_CR_PDS_CTRL_SOC_ENB_LEN) - 1) << PDS_CR_PDS_CTRL_SOC_ENB_POS))
#define PDS_CR_PDS_RST_SOC                    PDS_CR_PDS_RST_SOC
#define PDS_CR_PDS_RST_SOC_POS                (16U)
#define PDS_CR_PDS_RST_SOC_LEN                (1U)
#define PDS_CR_PDS_RST_SOC_MSK                (((1U << PDS_CR_PDS_RST_SOC_LEN) - 1) << PDS_CR_PDS_RST_SOC_POS)
#define PDS_CR_PDS_RST_SOC_UMSK               (~(((1U << PDS_CR_PDS_RST_SOC_LEN) - 1) << PDS_CR_PDS_RST_SOC_POS))
#define PDS_CR_PDS_RC32M_OFF_DIS              PDS_CR_PDS_RC32M_OFF_DIS
#define PDS_CR_PDS_RC32M_OFF_DIS_POS          (17U)
#define PDS_CR_PDS_RC32M_OFF_DIS_LEN          (1U)
#define PDS_CR_PDS_RC32M_OFF_DIS_MSK          (((1U << PDS_CR_PDS_RC32M_OFF_DIS_LEN) - 1) << PDS_CR_PDS_RC32M_OFF_DIS_POS)
#define PDS_CR_PDS_RC32M_OFF_DIS_UMSK         (~(((1U << PDS_CR_PDS_RC32M_OFF_DIS_LEN) - 1) << PDS_CR_PDS_RC32M_OFF_DIS_POS))
#define PDS_CR_PDS_LDO11_VSEL_EN              PDS_CR_PDS_LDO11_VSEL_EN
#define PDS_CR_PDS_LDO11_VSEL_EN_POS          (18U)
#define PDS_CR_PDS_LDO11_VSEL_EN_LEN          (1U)
#define PDS_CR_PDS_LDO11_VSEL_EN_MSK          (((1U << PDS_CR_PDS_LDO11_VSEL_EN_LEN) - 1) << PDS_CR_PDS_LDO11_VSEL_EN_POS)
#define PDS_CR_PDS_LDO11_VSEL_EN_UMSK         (~(((1U << PDS_CR_PDS_LDO11_VSEL_EN_LEN) - 1) << PDS_CR_PDS_LDO11_VSEL_EN_POS))
#define PDS_CR_PDS_CTRL_USBPLL_PD             PDS_CR_PDS_CTRL_USBPLL_PD
#define PDS_CR_PDS_CTRL_USBPLL_PD_POS         (19U)
#define PDS_CR_PDS_CTRL_USBPLL_PD_LEN         (1U)
#define PDS_CR_PDS_CTRL_USBPLL_PD_MSK         (((1U << PDS_CR_PDS_CTRL_USBPLL_PD_LEN) - 1) << PDS_CR_PDS_CTRL_USBPLL_PD_POS)
#define PDS_CR_PDS_CTRL_USBPLL_PD_UMSK        (~(((1U << PDS_CR_PDS_CTRL_USBPLL_PD_LEN) - 1) << PDS_CR_PDS_CTRL_USBPLL_PD_POS))
#define PDS_CR_PDS_CTRL_AUPLL_PD              PDS_CR_PDS_CTRL_AUPLL_PD
#define PDS_CR_PDS_CTRL_AUPLL_PD_POS          (20U)
#define PDS_CR_PDS_CTRL_AUPLL_PD_LEN          (1U)
#define PDS_CR_PDS_CTRL_AUPLL_PD_MSK          (((1U << PDS_CR_PDS_CTRL_AUPLL_PD_LEN) - 1) << PDS_CR_PDS_CTRL_AUPLL_PD_POS)
#define PDS_CR_PDS_CTRL_AUPLL_PD_UMSK         (~(((1U << PDS_CR_PDS_CTRL_AUPLL_PD_LEN) - 1) << PDS_CR_PDS_CTRL_AUPLL_PD_POS))
#define PDS_CR_PDS_CTRL_WIFIPLL_PD            PDS_CR_PDS_CTRL_WIFIPLL_PD
#define PDS_CR_PDS_CTRL_WIFIPLL_PD_POS        (22U)
#define PDS_CR_PDS_CTRL_WIFIPLL_PD_LEN        (1U)
#define PDS_CR_PDS_CTRL_WIFIPLL_PD_MSK        (((1U << PDS_CR_PDS_CTRL_WIFIPLL_PD_LEN) - 1) << PDS_CR_PDS_CTRL_WIFIPLL_PD_POS)
#define PDS_CR_PDS_CTRL_WIFIPLL_PD_UMSK       (~(((1U << PDS_CR_PDS_CTRL_WIFIPLL_PD_LEN) - 1) << PDS_CR_PDS_CTRL_WIFIPLL_PD_POS))
#define PDS_CR_PDS_LDO11_VOL                  PDS_CR_PDS_LDO11_VOL
#define PDS_CR_PDS_LDO11_VOL_POS              (23U)
#define PDS_CR_PDS_LDO11_VOL_LEN              (5U)
#define PDS_CR_PDS_LDO11_VOL_MSK              (((1U << PDS_CR_PDS_LDO11_VOL_LEN) - 1) << PDS_CR_PDS_LDO11_VOL_POS)
#define PDS_CR_PDS_LDO11_VOL_UMSK             (~(((1U << PDS_CR_PDS_LDO11_VOL_LEN) - 1) << PDS_CR_PDS_LDO11_VOL_POS))
#define PDS_CR_PDS_CTRL_RF                    PDS_CR_PDS_CTRL_RF
#define PDS_CR_PDS_CTRL_RF_POS                (28U)
#define PDS_CR_PDS_CTRL_RF_LEN                (2U)
#define PDS_CR_PDS_CTRL_RF_MSK                (((1U << PDS_CR_PDS_CTRL_RF_LEN) - 1) << PDS_CR_PDS_CTRL_RF_POS)
#define PDS_CR_PDS_CTRL_RF_UMSK               (~(((1U << PDS_CR_PDS_CTRL_RF_LEN) - 1) << PDS_CR_PDS_CTRL_RF_POS))
#define PDS_CR_PDS_START_USE_TBTT_SLEEP       PDS_CR_PDS_START_USE_TBTT_SLEEP
#define PDS_CR_PDS_START_USE_TBTT_SLEEP_POS   (30U)
#define PDS_CR_PDS_START_USE_TBTT_SLEEP_LEN   (1U)
#define PDS_CR_PDS_START_USE_TBTT_SLEEP_MSK   (((1U << PDS_CR_PDS_START_USE_TBTT_SLEEP_LEN) - 1) << PDS_CR_PDS_START_USE_TBTT_SLEEP_POS)
#define PDS_CR_PDS_START_USE_TBTT_SLEEP_UMSK  (~(((1U << PDS_CR_PDS_START_USE_TBTT_SLEEP_LEN) - 1) << PDS_CR_PDS_START_USE_TBTT_SLEEP_POS))
#define PDS_CR_PDS_GPIO_ISO_MODE              PDS_CR_PDS_GPIO_ISO_MODE
#define PDS_CR_PDS_GPIO_ISO_MODE_POS          (31U)
#define PDS_CR_PDS_GPIO_ISO_MODE_LEN          (1U)
#define PDS_CR_PDS_GPIO_ISO_MODE_MSK          (((1U << PDS_CR_PDS_GPIO_ISO_MODE_LEN) - 1) << PDS_CR_PDS_GPIO_ISO_MODE_POS)
#define PDS_CR_PDS_GPIO_ISO_MODE_UMSK         (~(((1U << PDS_CR_PDS_GPIO_ISO_MODE_LEN) - 1) << PDS_CR_PDS_GPIO_ISO_MODE_POS))

/* 0x4 : PDS_TIME1 */
#define PDS_TIME1_OFFSET           (0x4)
#define PDS_CR_SLEEP_DURATION      PDS_CR_SLEEP_DURATION
#define PDS_CR_SLEEP_DURATION_POS  (0U)
#define PDS_CR_SLEEP_DURATION_LEN  (32U)
#define PDS_CR_SLEEP_DURATION_MSK  (((1U << PDS_CR_SLEEP_DURATION_LEN) - 1) << PDS_CR_SLEEP_DURATION_POS)
#define PDS_CR_SLEEP_DURATION_UMSK (~(((1U << PDS_CR_SLEEP_DURATION_LEN) - 1) << PDS_CR_SLEEP_DURATION_POS))

/* 0xC : PDS_INT */
#define PDS_INT_OFFSET                            (0xC)
#define PDS_RO_PDS_WAKE_INT                       PDS_RO_PDS_WAKE_INT
#define PDS_RO_PDS_WAKE_INT_POS                   (0U)
#define PDS_RO_PDS_WAKE_INT_LEN                   (1U)
#define PDS_RO_PDS_WAKE_INT_MSK                   (((1U << PDS_RO_PDS_WAKE_INT_LEN) - 1) << PDS_RO_PDS_WAKE_INT_POS)
#define PDS_RO_PDS_WAKE_INT_UMSK                  (~(((1U << PDS_RO_PDS_WAKE_INT_LEN) - 1) << PDS_RO_PDS_WAKE_INT_POS))
#define PDS_RO_PDS_RF_DONE_INT                    PDS_RO_PDS_RF_DONE_INT
#define PDS_RO_PDS_RF_DONE_INT_POS                (1U)
#define PDS_RO_PDS_RF_DONE_INT_LEN                (1U)
#define PDS_RO_PDS_RF_DONE_INT_MSK                (((1U << PDS_RO_PDS_RF_DONE_INT_LEN) - 1) << PDS_RO_PDS_RF_DONE_INT_POS)
#define PDS_RO_PDS_RF_DONE_INT_UMSK               (~(((1U << PDS_RO_PDS_RF_DONE_INT_LEN) - 1) << PDS_RO_PDS_RF_DONE_INT_POS))
#define PDS_RO_PDS_WIFI_TBTT_SLEEP_IRQ            PDS_RO_PDS_WIFI_TBTT_SLEEP_IRQ
#define PDS_RO_PDS_WIFI_TBTT_SLEEP_IRQ_POS        (2U)
#define PDS_RO_PDS_WIFI_TBTT_SLEEP_IRQ_LEN        (1U)
#define PDS_RO_PDS_WIFI_TBTT_SLEEP_IRQ_MSK        (((1U << PDS_RO_PDS_WIFI_TBTT_SLEEP_IRQ_LEN) - 1) << PDS_RO_PDS_WIFI_TBTT_SLEEP_IRQ_POS)
#define PDS_RO_PDS_WIFI_TBTT_SLEEP_IRQ_UMSK       (~(((1U << PDS_RO_PDS_WIFI_TBTT_SLEEP_IRQ_LEN) - 1) << PDS_RO_PDS_WIFI_TBTT_SLEEP_IRQ_POS))
#define PDS_RO_PDS_WIFI_TBTT_WAKEUP_IRQ           PDS_RO_PDS_WIFI_TBTT_WAKEUP_IRQ
#define PDS_RO_PDS_WIFI_TBTT_WAKEUP_IRQ_POS       (3U)
#define PDS_RO_PDS_WIFI_TBTT_WAKEUP_IRQ_LEN       (1U)
#define PDS_RO_PDS_WIFI_TBTT_WAKEUP_IRQ_MSK       (((1U << PDS_RO_PDS_WIFI_TBTT_WAKEUP_IRQ_LEN) - 1) << PDS_RO_PDS_WIFI_TBTT_WAKEUP_IRQ_POS)
#define PDS_RO_PDS_WIFI_TBTT_WAKEUP_IRQ_UMSK      (~(((1U << PDS_RO_PDS_WIFI_TBTT_WAKEUP_IRQ_LEN) - 1) << PDS_RO_PDS_WIFI_TBTT_WAKEUP_IRQ_POS))
#define PDS_CR_PDS_WAKE_INT_MASK                  PDS_CR_PDS_WAKE_INT_MASK
#define PDS_CR_PDS_WAKE_INT_MASK_POS              (4U)
#define PDS_CR_PDS_WAKE_INT_MASK_LEN              (1U)
#define PDS_CR_PDS_WAKE_INT_MASK_MSK              (((1U << PDS_CR_PDS_WAKE_INT_MASK_LEN) - 1) << PDS_CR_PDS_WAKE_INT_MASK_POS)
#define PDS_CR_PDS_WAKE_INT_MASK_UMSK             (~(((1U << PDS_CR_PDS_WAKE_INT_MASK_LEN) - 1) << PDS_CR_PDS_WAKE_INT_MASK_POS))
#define PDS_CR_PDS_RF_DONE_INT_MASK               PDS_CR_PDS_RF_DONE_INT_MASK
#define PDS_CR_PDS_RF_DONE_INT_MASK_POS           (5U)
#define PDS_CR_PDS_RF_DONE_INT_MASK_LEN           (1U)
#define PDS_CR_PDS_RF_DONE_INT_MASK_MSK           (((1U << PDS_CR_PDS_RF_DONE_INT_MASK_LEN) - 1) << PDS_CR_PDS_RF_DONE_INT_MASK_POS)
#define PDS_CR_PDS_RF_DONE_INT_MASK_UMSK          (~(((1U << PDS_CR_PDS_RF_DONE_INT_MASK_LEN) - 1) << PDS_CR_PDS_RF_DONE_INT_MASK_POS))
#define PDS_CR_PDS_WIFI_TBTT_SLEEP_IRQ_MASK       PDS_CR_PDS_WIFI_TBTT_SLEEP_IRQ_MASK
#define PDS_CR_PDS_WIFI_TBTT_SLEEP_IRQ_MASK_POS   (6U)
#define PDS_CR_PDS_WIFI_TBTT_SLEEP_IRQ_MASK_LEN   (1U)
#define PDS_CR_PDS_WIFI_TBTT_SLEEP_IRQ_MASK_MSK   (((1U << PDS_CR_PDS_WIFI_TBTT_SLEEP_IRQ_MASK_LEN) - 1) << PDS_CR_PDS_WIFI_TBTT_SLEEP_IRQ_MASK_POS)
#define PDS_CR_PDS_WIFI_TBTT_SLEEP_IRQ_MASK_UMSK  (~(((1U << PDS_CR_PDS_WIFI_TBTT_SLEEP_IRQ_MASK_LEN) - 1) << PDS_CR_PDS_WIFI_TBTT_SLEEP_IRQ_MASK_POS))
#define PDS_CR_PDS_WIFI_TBTT_WAKEUP_IRQ_MASK      PDS_CR_PDS_WIFI_TBTT_WAKEUP_IRQ_MASK
#define PDS_CR_PDS_WIFI_TBTT_WAKEUP_IRQ_MASK_POS  (7U)
#define PDS_CR_PDS_WIFI_TBTT_WAKEUP_IRQ_MASK_LEN  (1U)
#define PDS_CR_PDS_WIFI_TBTT_WAKEUP_IRQ_MASK_MSK  (((1U << PDS_CR_PDS_WIFI_TBTT_WAKEUP_IRQ_MASK_LEN) - 1) << PDS_CR_PDS_WIFI_TBTT_WAKEUP_IRQ_MASK_POS)
#define PDS_CR_PDS_WIFI_TBTT_WAKEUP_IRQ_MASK_UMSK (~(((1U << PDS_CR_PDS_WIFI_TBTT_WAKEUP_IRQ_MASK_LEN) - 1) << PDS_CR_PDS_WIFI_TBTT_WAKEUP_IRQ_MASK_POS))
#define PDS_CR_PDS_INT_CLR                        PDS_CR_PDS_INT_CLR
#define PDS_CR_PDS_INT_CLR_POS                    (8U)
#define PDS_CR_PDS_INT_CLR_LEN                    (1U)
#define PDS_CR_PDS_INT_CLR_MSK                    (((1U << PDS_CR_PDS_INT_CLR_LEN) - 1) << PDS_CR_PDS_INT_CLR_POS)
#define PDS_CR_PDS_INT_CLR_UMSK                   (~(((1U << PDS_CR_PDS_INT_CLR_LEN) - 1) << PDS_CR_PDS_INT_CLR_POS))
#define PDS_CR_PDS_WAKEUP_SRC_EN                  PDS_CR_PDS_WAKEUP_SRC_EN
#define PDS_CR_PDS_WAKEUP_SRC_EN_POS              (10U)
#define PDS_CR_PDS_WAKEUP_SRC_EN_LEN              (10U)
#define PDS_CR_PDS_WAKEUP_SRC_EN_MSK              (((1U << PDS_CR_PDS_WAKEUP_SRC_EN_LEN) - 1) << PDS_CR_PDS_WAKEUP_SRC_EN_POS)
#define PDS_CR_PDS_WAKEUP_SRC_EN_UMSK             (~(((1U << PDS_CR_PDS_WAKEUP_SRC_EN_LEN) - 1) << PDS_CR_PDS_WAKEUP_SRC_EN_POS))
#define PDS_RO_PDS_WAKEUP_EVENT                   PDS_RO_PDS_WAKEUP_EVENT
#define PDS_RO_PDS_WAKEUP_EVENT_POS               (21U)
#define PDS_RO_PDS_WAKEUP_EVENT_LEN               (10U)
#define PDS_RO_PDS_WAKEUP_EVENT_MSK               (((1U << PDS_RO_PDS_WAKEUP_EVENT_LEN) - 1) << PDS_RO_PDS_WAKEUP_EVENT_POS)
#define PDS_RO_PDS_WAKEUP_EVENT_UMSK              (~(((1U << PDS_RO_PDS_WAKEUP_EVENT_LEN) - 1) << PDS_RO_PDS_WAKEUP_EVENT_POS))

/* 0x10 : PDS_CTL2 */
#define PDS_CTL2_OFFSET                    (0x10)
#define PDS_CR_PDS_FORCE_NP_PWR_OFF        PDS_CR_PDS_FORCE_NP_PWR_OFF
#define PDS_CR_PDS_FORCE_NP_PWR_OFF_POS    (0U)
#define PDS_CR_PDS_FORCE_NP_PWR_OFF_LEN    (1U)
#define PDS_CR_PDS_FORCE_NP_PWR_OFF_MSK    (((1U << PDS_CR_PDS_FORCE_NP_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_NP_PWR_OFF_POS)
#define PDS_CR_PDS_FORCE_NP_PWR_OFF_UMSK   (~(((1U << PDS_CR_PDS_FORCE_NP_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_NP_PWR_OFF_POS))
#define PDS_CR_PDS_FORCE_WB_PWR_OFF        PDS_CR_PDS_FORCE_WB_PWR_OFF
#define PDS_CR_PDS_FORCE_WB_PWR_OFF_POS    (2U)
#define PDS_CR_PDS_FORCE_WB_PWR_OFF_LEN    (1U)
#define PDS_CR_PDS_FORCE_WB_PWR_OFF_MSK    (((1U << PDS_CR_PDS_FORCE_WB_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_WB_PWR_OFF_POS)
#define PDS_CR_PDS_FORCE_WB_PWR_OFF_UMSK   (~(((1U << PDS_CR_PDS_FORCE_WB_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_WB_PWR_OFF_POS))
#define PDS_CR_PDS_FORCE_USB_PWR_OFF       PDS_CR_PDS_FORCE_USB_PWR_OFF
#define PDS_CR_PDS_FORCE_USB_PWR_OFF_POS   (3U)
#define PDS_CR_PDS_FORCE_USB_PWR_OFF_LEN   (1U)
#define PDS_CR_PDS_FORCE_USB_PWR_OFF_MSK   (((1U << PDS_CR_PDS_FORCE_USB_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_USB_PWR_OFF_POS)
#define PDS_CR_PDS_FORCE_USB_PWR_OFF_UMSK  (~(((1U << PDS_CR_PDS_FORCE_USB_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_USB_PWR_OFF_POS))
#define PDS_CR_PDS_FORCE_NP_ISO_EN         PDS_CR_PDS_FORCE_NP_ISO_EN
#define PDS_CR_PDS_FORCE_NP_ISO_EN_POS     (4U)
#define PDS_CR_PDS_FORCE_NP_ISO_EN_LEN     (1U)
#define PDS_CR_PDS_FORCE_NP_ISO_EN_MSK     (((1U << PDS_CR_PDS_FORCE_NP_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_NP_ISO_EN_POS)
#define PDS_CR_PDS_FORCE_NP_ISO_EN_UMSK    (~(((1U << PDS_CR_PDS_FORCE_NP_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_NP_ISO_EN_POS))
#define PDS_CR_PDS_FORCE_WB_ISO_EN         PDS_CR_PDS_FORCE_WB_ISO_EN
#define PDS_CR_PDS_FORCE_WB_ISO_EN_POS     (6U)
#define PDS_CR_PDS_FORCE_WB_ISO_EN_LEN     (1U)
#define PDS_CR_PDS_FORCE_WB_ISO_EN_MSK     (((1U << PDS_CR_PDS_FORCE_WB_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_WB_ISO_EN_POS)
#define PDS_CR_PDS_FORCE_WB_ISO_EN_UMSK    (~(((1U << PDS_CR_PDS_FORCE_WB_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_WB_ISO_EN_POS))
#define PDS_CR_PDS_FORCE_USB_ISO_EN        PDS_CR_PDS_FORCE_USB_ISO_EN
#define PDS_CR_PDS_FORCE_USB_ISO_EN_POS    (7U)
#define PDS_CR_PDS_FORCE_USB_ISO_EN_LEN    (1U)
#define PDS_CR_PDS_FORCE_USB_ISO_EN_MSK    (((1U << PDS_CR_PDS_FORCE_USB_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_USB_ISO_EN_POS)
#define PDS_CR_PDS_FORCE_USB_ISO_EN_UMSK   (~(((1U << PDS_CR_PDS_FORCE_USB_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_USB_ISO_EN_POS))
#define PDS_CR_PDS_FORCE_NP_PDS_RST        PDS_CR_PDS_FORCE_NP_PDS_RST
#define PDS_CR_PDS_FORCE_NP_PDS_RST_POS    (8U)
#define PDS_CR_PDS_FORCE_NP_PDS_RST_LEN    (1U)
#define PDS_CR_PDS_FORCE_NP_PDS_RST_MSK    (((1U << PDS_CR_PDS_FORCE_NP_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_NP_PDS_RST_POS)
#define PDS_CR_PDS_FORCE_NP_PDS_RST_UMSK   (~(((1U << PDS_CR_PDS_FORCE_NP_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_NP_PDS_RST_POS))
#define PDS_CR_PDS_FORCE_WB_PDS_RST        PDS_CR_PDS_FORCE_WB_PDS_RST
#define PDS_CR_PDS_FORCE_WB_PDS_RST_POS    (10U)
#define PDS_CR_PDS_FORCE_WB_PDS_RST_LEN    (1U)
#define PDS_CR_PDS_FORCE_WB_PDS_RST_MSK    (((1U << PDS_CR_PDS_FORCE_WB_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_WB_PDS_RST_POS)
#define PDS_CR_PDS_FORCE_WB_PDS_RST_UMSK   (~(((1U << PDS_CR_PDS_FORCE_WB_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_WB_PDS_RST_POS))
#define PDS_CR_PDS_FORCE_USB_PDS_RST       PDS_CR_PDS_FORCE_USB_PDS_RST
#define PDS_CR_PDS_FORCE_USB_PDS_RST_POS   (11U)
#define PDS_CR_PDS_FORCE_USB_PDS_RST_LEN   (1U)
#define PDS_CR_PDS_FORCE_USB_PDS_RST_MSK   (((1U << PDS_CR_PDS_FORCE_USB_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_USB_PDS_RST_POS)
#define PDS_CR_PDS_FORCE_USB_PDS_RST_UMSK  (~(((1U << PDS_CR_PDS_FORCE_USB_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_USB_PDS_RST_POS))
#define PDS_CR_PDS_FORCE_NP_MEM_STBY       PDS_CR_PDS_FORCE_NP_MEM_STBY
#define PDS_CR_PDS_FORCE_NP_MEM_STBY_POS   (12U)
#define PDS_CR_PDS_FORCE_NP_MEM_STBY_LEN   (1U)
#define PDS_CR_PDS_FORCE_NP_MEM_STBY_MSK   (((1U << PDS_CR_PDS_FORCE_NP_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_NP_MEM_STBY_POS)
#define PDS_CR_PDS_FORCE_NP_MEM_STBY_UMSK  (~(((1U << PDS_CR_PDS_FORCE_NP_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_NP_MEM_STBY_POS))
#define PDS_CR_PDS_FORCE_WB_MEM_STBY       PDS_CR_PDS_FORCE_WB_MEM_STBY
#define PDS_CR_PDS_FORCE_WB_MEM_STBY_POS   (14U)
#define PDS_CR_PDS_FORCE_WB_MEM_STBY_LEN   (1U)
#define PDS_CR_PDS_FORCE_WB_MEM_STBY_MSK   (((1U << PDS_CR_PDS_FORCE_WB_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_WB_MEM_STBY_POS)
#define PDS_CR_PDS_FORCE_WB_MEM_STBY_UMSK  (~(((1U << PDS_CR_PDS_FORCE_WB_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_WB_MEM_STBY_POS))
#define PDS_CR_PDS_FORCE_USB_MEM_STBY      PDS_CR_PDS_FORCE_USB_MEM_STBY
#define PDS_CR_PDS_FORCE_USB_MEM_STBY_POS  (15U)
#define PDS_CR_PDS_FORCE_USB_MEM_STBY_LEN  (1U)
#define PDS_CR_PDS_FORCE_USB_MEM_STBY_MSK  (((1U << PDS_CR_PDS_FORCE_USB_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_USB_MEM_STBY_POS)
#define PDS_CR_PDS_FORCE_USB_MEM_STBY_UMSK (~(((1U << PDS_CR_PDS_FORCE_USB_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_USB_MEM_STBY_POS))
#define PDS_CR_PDS_FORCE_NP_GATE_CLK       PDS_CR_PDS_FORCE_NP_GATE_CLK
#define PDS_CR_PDS_FORCE_NP_GATE_CLK_POS   (16U)
#define PDS_CR_PDS_FORCE_NP_GATE_CLK_LEN   (1U)
#define PDS_CR_PDS_FORCE_NP_GATE_CLK_MSK   (((1U << PDS_CR_PDS_FORCE_NP_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_NP_GATE_CLK_POS)
#define PDS_CR_PDS_FORCE_NP_GATE_CLK_UMSK  (~(((1U << PDS_CR_PDS_FORCE_NP_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_NP_GATE_CLK_POS))
#define PDS_CR_PDS_FORCE_WB_GATE_CLK       PDS_CR_PDS_FORCE_WB_GATE_CLK
#define PDS_CR_PDS_FORCE_WB_GATE_CLK_POS   (18U)
#define PDS_CR_PDS_FORCE_WB_GATE_CLK_LEN   (1U)
#define PDS_CR_PDS_FORCE_WB_GATE_CLK_MSK   (((1U << PDS_CR_PDS_FORCE_WB_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_WB_GATE_CLK_POS)
#define PDS_CR_PDS_FORCE_WB_GATE_CLK_UMSK  (~(((1U << PDS_CR_PDS_FORCE_WB_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_WB_GATE_CLK_POS))
#define PDS_CR_PDS_FORCE_USB_GATE_CLK      PDS_CR_PDS_FORCE_USB_GATE_CLK
#define PDS_CR_PDS_FORCE_USB_GATE_CLK_POS  (19U)
#define PDS_CR_PDS_FORCE_USB_GATE_CLK_LEN  (1U)
#define PDS_CR_PDS_FORCE_USB_GATE_CLK_MSK  (((1U << PDS_CR_PDS_FORCE_USB_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_USB_GATE_CLK_POS)
#define PDS_CR_PDS_FORCE_USB_GATE_CLK_UMSK (~(((1U << PDS_CR_PDS_FORCE_USB_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_USB_GATE_CLK_POS))

/* 0x14 : PDS_CTL3 */
#define PDS_CTL3_OFFSET                     (0x14)
#define PDS_CR_PDS_FORCE_MISC_PWR_OFF       PDS_CR_PDS_FORCE_MISC_PWR_OFF
#define PDS_CR_PDS_FORCE_MISC_PWR_OFF_POS   (1U)
#define PDS_CR_PDS_FORCE_MISC_PWR_OFF_LEN   (1U)
#define PDS_CR_PDS_FORCE_MISC_PWR_OFF_MSK   (((1U << PDS_CR_PDS_FORCE_MISC_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_PWR_OFF_POS)
#define PDS_CR_PDS_FORCE_MISC_PWR_OFF_UMSK  (~(((1U << PDS_CR_PDS_FORCE_MISC_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_PWR_OFF_POS))
#define PDS_CR_PDS_FORCE_MISC_ISO_EN        PDS_CR_PDS_FORCE_MISC_ISO_EN
#define PDS_CR_PDS_FORCE_MISC_ISO_EN_POS    (4U)
#define PDS_CR_PDS_FORCE_MISC_ISO_EN_LEN    (1U)
#define PDS_CR_PDS_FORCE_MISC_ISO_EN_MSK    (((1U << PDS_CR_PDS_FORCE_MISC_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_ISO_EN_POS)
#define PDS_CR_PDS_FORCE_MISC_ISO_EN_UMSK   (~(((1U << PDS_CR_PDS_FORCE_MISC_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_ISO_EN_POS))
#define PDS_CR_PDS_FORCE_MISC_PDS_RST       PDS_CR_PDS_FORCE_MISC_PDS_RST
#define PDS_CR_PDS_FORCE_MISC_PDS_RST_POS   (7U)
#define PDS_CR_PDS_FORCE_MISC_PDS_RST_LEN   (1U)
#define PDS_CR_PDS_FORCE_MISC_PDS_RST_MSK   (((1U << PDS_CR_PDS_FORCE_MISC_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_PDS_RST_POS)
#define PDS_CR_PDS_FORCE_MISC_PDS_RST_UMSK  (~(((1U << PDS_CR_PDS_FORCE_MISC_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_PDS_RST_POS))
#define PDS_CR_PDS_FORCE_MISC_MEM_STBY      PDS_CR_PDS_FORCE_MISC_MEM_STBY
#define PDS_CR_PDS_FORCE_MISC_MEM_STBY_POS  (10U)
#define PDS_CR_PDS_FORCE_MISC_MEM_STBY_LEN  (1U)
#define PDS_CR_PDS_FORCE_MISC_MEM_STBY_MSK  (((1U << PDS_CR_PDS_FORCE_MISC_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_MEM_STBY_POS)
#define PDS_CR_PDS_FORCE_MISC_MEM_STBY_UMSK (~(((1U << PDS_CR_PDS_FORCE_MISC_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_MEM_STBY_POS))
#define PDS_CR_PDS_FORCE_MISC_GATE_CLK      PDS_CR_PDS_FORCE_MISC_GATE_CLK
#define PDS_CR_PDS_FORCE_MISC_GATE_CLK_POS  (13U)
#define PDS_CR_PDS_FORCE_MISC_GATE_CLK_LEN  (1U)
#define PDS_CR_PDS_FORCE_MISC_GATE_CLK_MSK  (((1U << PDS_CR_PDS_FORCE_MISC_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_GATE_CLK_POS)
#define PDS_CR_PDS_FORCE_MISC_GATE_CLK_UMSK (~(((1U << PDS_CR_PDS_FORCE_MISC_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_GATE_CLK_POS))
#define PDS_CR_PDS_NP_ISO_EN                PDS_CR_PDS_NP_ISO_EN
#define PDS_CR_PDS_NP_ISO_EN_POS            (24U)
#define PDS_CR_PDS_NP_ISO_EN_LEN            (1U)
#define PDS_CR_PDS_NP_ISO_EN_MSK            (((1U << PDS_CR_PDS_NP_ISO_EN_LEN) - 1) << PDS_CR_PDS_NP_ISO_EN_POS)
#define PDS_CR_PDS_NP_ISO_EN_UMSK           (~(((1U << PDS_CR_PDS_NP_ISO_EN_LEN) - 1) << PDS_CR_PDS_NP_ISO_EN_POS))
#define PDS_CR_PDS_WB_ISO_EN                PDS_CR_PDS_WB_ISO_EN
#define PDS_CR_PDS_WB_ISO_EN_POS            (27U)
#define PDS_CR_PDS_WB_ISO_EN_LEN            (1U)
#define PDS_CR_PDS_WB_ISO_EN_MSK            (((1U << PDS_CR_PDS_WB_ISO_EN_LEN) - 1) << PDS_CR_PDS_WB_ISO_EN_POS)
#define PDS_CR_PDS_WB_ISO_EN_UMSK           (~(((1U << PDS_CR_PDS_WB_ISO_EN_LEN) - 1) << PDS_CR_PDS_WB_ISO_EN_POS))
#define PDS_CR_PDS_USB_ISO_EN               PDS_CR_PDS_USB_ISO_EN
#define PDS_CR_PDS_USB_ISO_EN_POS           (29U)
#define PDS_CR_PDS_USB_ISO_EN_LEN           (1U)
#define PDS_CR_PDS_USB_ISO_EN_MSK           (((1U << PDS_CR_PDS_USB_ISO_EN_LEN) - 1) << PDS_CR_PDS_USB_ISO_EN_POS)
#define PDS_CR_PDS_USB_ISO_EN_UMSK          (~(((1U << PDS_CR_PDS_USB_ISO_EN_LEN) - 1) << PDS_CR_PDS_USB_ISO_EN_POS))
#define PDS_CR_PDS_MISC_ISO_EN              PDS_CR_PDS_MISC_ISO_EN
#define PDS_CR_PDS_MISC_ISO_EN_POS          (30U)
#define PDS_CR_PDS_MISC_ISO_EN_LEN          (1U)
#define PDS_CR_PDS_MISC_ISO_EN_MSK          (((1U << PDS_CR_PDS_MISC_ISO_EN_LEN) - 1) << PDS_CR_PDS_MISC_ISO_EN_POS)
#define PDS_CR_PDS_MISC_ISO_EN_UMSK         (~(((1U << PDS_CR_PDS_MISC_ISO_EN_LEN) - 1) << PDS_CR_PDS_MISC_ISO_EN_POS))

/* 0x18 : PDS_CTL4 */
#define PDS_CTL4_OFFSET               (0x18)
#define PDS_CR_PDS_NP_PWR_OFF         PDS_CR_PDS_NP_PWR_OFF
#define PDS_CR_PDS_NP_PWR_OFF_POS     (0U)
#define PDS_CR_PDS_NP_PWR_OFF_LEN     (1U)
#define PDS_CR_PDS_NP_PWR_OFF_MSK     (((1U << PDS_CR_PDS_NP_PWR_OFF_LEN) - 1) << PDS_CR_PDS_NP_PWR_OFF_POS)
#define PDS_CR_PDS_NP_PWR_OFF_UMSK    (~(((1U << PDS_CR_PDS_NP_PWR_OFF_LEN) - 1) << PDS_CR_PDS_NP_PWR_OFF_POS))
#define PDS_CR_PDS_NP_RESET           PDS_CR_PDS_NP_RESET
#define PDS_CR_PDS_NP_RESET_POS       (1U)
#define PDS_CR_PDS_NP_RESET_LEN       (1U)
#define PDS_CR_PDS_NP_RESET_MSK       (((1U << PDS_CR_PDS_NP_RESET_LEN) - 1) << PDS_CR_PDS_NP_RESET_POS)
#define PDS_CR_PDS_NP_RESET_UMSK      (~(((1U << PDS_CR_PDS_NP_RESET_LEN) - 1) << PDS_CR_PDS_NP_RESET_POS))
#define PDS_CR_PDS_NP_MEM_STBY        PDS_CR_PDS_NP_MEM_STBY
#define PDS_CR_PDS_NP_MEM_STBY_POS    (2U)
#define PDS_CR_PDS_NP_MEM_STBY_LEN    (1U)
#define PDS_CR_PDS_NP_MEM_STBY_MSK    (((1U << PDS_CR_PDS_NP_MEM_STBY_LEN) - 1) << PDS_CR_PDS_NP_MEM_STBY_POS)
#define PDS_CR_PDS_NP_MEM_STBY_UMSK   (~(((1U << PDS_CR_PDS_NP_MEM_STBY_LEN) - 1) << PDS_CR_PDS_NP_MEM_STBY_POS))
#define PDS_CR_PDS_NP_GATE_CLK        PDS_CR_PDS_NP_GATE_CLK
#define PDS_CR_PDS_NP_GATE_CLK_POS    (3U)
#define PDS_CR_PDS_NP_GATE_CLK_LEN    (1U)
#define PDS_CR_PDS_NP_GATE_CLK_MSK    (((1U << PDS_CR_PDS_NP_GATE_CLK_LEN) - 1) << PDS_CR_PDS_NP_GATE_CLK_POS)
#define PDS_CR_PDS_NP_GATE_CLK_UMSK   (~(((1U << PDS_CR_PDS_NP_GATE_CLK_LEN) - 1) << PDS_CR_PDS_NP_GATE_CLK_POS))
#define PDS_CR_PDS_WB_PWR_OFF         PDS_CR_PDS_WB_PWR_OFF
#define PDS_CR_PDS_WB_PWR_OFF_POS     (12U)
#define PDS_CR_PDS_WB_PWR_OFF_LEN     (1U)
#define PDS_CR_PDS_WB_PWR_OFF_MSK     (((1U << PDS_CR_PDS_WB_PWR_OFF_LEN) - 1) << PDS_CR_PDS_WB_PWR_OFF_POS)
#define PDS_CR_PDS_WB_PWR_OFF_UMSK    (~(((1U << PDS_CR_PDS_WB_PWR_OFF_LEN) - 1) << PDS_CR_PDS_WB_PWR_OFF_POS))
#define PDS_CR_PDS_WB_RESET           PDS_CR_PDS_WB_RESET
#define PDS_CR_PDS_WB_RESET_POS       (13U)
#define PDS_CR_PDS_WB_RESET_LEN       (1U)
#define PDS_CR_PDS_WB_RESET_MSK       (((1U << PDS_CR_PDS_WB_RESET_LEN) - 1) << PDS_CR_PDS_WB_RESET_POS)
#define PDS_CR_PDS_WB_RESET_UMSK      (~(((1U << PDS_CR_PDS_WB_RESET_LEN) - 1) << PDS_CR_PDS_WB_RESET_POS))
#define PDS_CR_PDS_WB_MEM_STBY        PDS_CR_PDS_WB_MEM_STBY
#define PDS_CR_PDS_WB_MEM_STBY_POS    (14U)
#define PDS_CR_PDS_WB_MEM_STBY_LEN    (1U)
#define PDS_CR_PDS_WB_MEM_STBY_MSK    (((1U << PDS_CR_PDS_WB_MEM_STBY_LEN) - 1) << PDS_CR_PDS_WB_MEM_STBY_POS)
#define PDS_CR_PDS_WB_MEM_STBY_UMSK   (~(((1U << PDS_CR_PDS_WB_MEM_STBY_LEN) - 1) << PDS_CR_PDS_WB_MEM_STBY_POS))
#define PDS_CR_PDS_WB_GATE_CLK        PDS_CR_PDS_WB_GATE_CLK
#define PDS_CR_PDS_WB_GATE_CLK_POS    (15U)
#define PDS_CR_PDS_WB_GATE_CLK_LEN    (1U)
#define PDS_CR_PDS_WB_GATE_CLK_MSK    (((1U << PDS_CR_PDS_WB_GATE_CLK_LEN) - 1) << PDS_CR_PDS_WB_GATE_CLK_POS)
#define PDS_CR_PDS_WB_GATE_CLK_UMSK   (~(((1U << PDS_CR_PDS_WB_GATE_CLK_LEN) - 1) << PDS_CR_PDS_WB_GATE_CLK_POS))
#define PDS_CR_PDS_USB_PWR_OFF        PDS_CR_PDS_USB_PWR_OFF
#define PDS_CR_PDS_USB_PWR_OFF_POS    (20U)
#define PDS_CR_PDS_USB_PWR_OFF_LEN    (1U)
#define PDS_CR_PDS_USB_PWR_OFF_MSK    (((1U << PDS_CR_PDS_USB_PWR_OFF_LEN) - 1) << PDS_CR_PDS_USB_PWR_OFF_POS)
#define PDS_CR_PDS_USB_PWR_OFF_UMSK   (~(((1U << PDS_CR_PDS_USB_PWR_OFF_LEN) - 1) << PDS_CR_PDS_USB_PWR_OFF_POS))
#define PDS_CR_PDS_USB_RESET          PDS_CR_PDS_USB_RESET
#define PDS_CR_PDS_USB_RESET_POS      (21U)
#define PDS_CR_PDS_USB_RESET_LEN      (1U)
#define PDS_CR_PDS_USB_RESET_MSK      (((1U << PDS_CR_PDS_USB_RESET_LEN) - 1) << PDS_CR_PDS_USB_RESET_POS)
#define PDS_CR_PDS_USB_RESET_UMSK     (~(((1U << PDS_CR_PDS_USB_RESET_LEN) - 1) << PDS_CR_PDS_USB_RESET_POS))
#define PDS_CR_PDS_USB_MEM_STBY       PDS_CR_PDS_USB_MEM_STBY
#define PDS_CR_PDS_USB_MEM_STBY_POS   (22U)
#define PDS_CR_PDS_USB_MEM_STBY_LEN   (1U)
#define PDS_CR_PDS_USB_MEM_STBY_MSK   (((1U << PDS_CR_PDS_USB_MEM_STBY_LEN) - 1) << PDS_CR_PDS_USB_MEM_STBY_POS)
#define PDS_CR_PDS_USB_MEM_STBY_UMSK  (~(((1U << PDS_CR_PDS_USB_MEM_STBY_LEN) - 1) << PDS_CR_PDS_USB_MEM_STBY_POS))
#define PDS_CR_PDS_USB_GATE_CLK       PDS_CR_PDS_USB_GATE_CLK
#define PDS_CR_PDS_USB_GATE_CLK_POS   (23U)
#define PDS_CR_PDS_USB_GATE_CLK_LEN   (1U)
#define PDS_CR_PDS_USB_GATE_CLK_MSK   (((1U << PDS_CR_PDS_USB_GATE_CLK_LEN) - 1) << PDS_CR_PDS_USB_GATE_CLK_POS)
#define PDS_CR_PDS_USB_GATE_CLK_UMSK  (~(((1U << PDS_CR_PDS_USB_GATE_CLK_LEN) - 1) << PDS_CR_PDS_USB_GATE_CLK_POS))
#define PDS_CR_PDS_MISC_PWR_OFF       PDS_CR_PDS_MISC_PWR_OFF
#define PDS_CR_PDS_MISC_PWR_OFF_POS   (24U)
#define PDS_CR_PDS_MISC_PWR_OFF_LEN   (1U)
#define PDS_CR_PDS_MISC_PWR_OFF_MSK   (((1U << PDS_CR_PDS_MISC_PWR_OFF_LEN) - 1) << PDS_CR_PDS_MISC_PWR_OFF_POS)
#define PDS_CR_PDS_MISC_PWR_OFF_UMSK  (~(((1U << PDS_CR_PDS_MISC_PWR_OFF_LEN) - 1) << PDS_CR_PDS_MISC_PWR_OFF_POS))
#define PDS_CR_PDS_MISC_RESET         PDS_CR_PDS_MISC_RESET
#define PDS_CR_PDS_MISC_RESET_POS     (25U)
#define PDS_CR_PDS_MISC_RESET_LEN     (1U)
#define PDS_CR_PDS_MISC_RESET_MSK     (((1U << PDS_CR_PDS_MISC_RESET_LEN) - 1) << PDS_CR_PDS_MISC_RESET_POS)
#define PDS_CR_PDS_MISC_RESET_UMSK    (~(((1U << PDS_CR_PDS_MISC_RESET_LEN) - 1) << PDS_CR_PDS_MISC_RESET_POS))
#define PDS_CR_PDS_MISC_MEM_STBY      PDS_CR_PDS_MISC_MEM_STBY
#define PDS_CR_PDS_MISC_MEM_STBY_POS  (26U)
#define PDS_CR_PDS_MISC_MEM_STBY_LEN  (1U)
#define PDS_CR_PDS_MISC_MEM_STBY_MSK  (((1U << PDS_CR_PDS_MISC_MEM_STBY_LEN) - 1) << PDS_CR_PDS_MISC_MEM_STBY_POS)
#define PDS_CR_PDS_MISC_MEM_STBY_UMSK (~(((1U << PDS_CR_PDS_MISC_MEM_STBY_LEN) - 1) << PDS_CR_PDS_MISC_MEM_STBY_POS))
#define PDS_CR_PDS_MISC_GATE_CLK      PDS_CR_PDS_MISC_GATE_CLK
#define PDS_CR_PDS_MISC_GATE_CLK_POS  (27U)
#define PDS_CR_PDS_MISC_GATE_CLK_LEN  (1U)
#define PDS_CR_PDS_MISC_GATE_CLK_MSK  (((1U << PDS_CR_PDS_MISC_GATE_CLK_LEN) - 1) << PDS_CR_PDS_MISC_GATE_CLK_POS)
#define PDS_CR_PDS_MISC_GATE_CLK_UMSK (~(((1U << PDS_CR_PDS_MISC_GATE_CLK_LEN) - 1) << PDS_CR_PDS_MISC_GATE_CLK_POS))

/* 0x1C : pds_stat */
#define PDS_STAT_OFFSET          (0x1C)
#define PDS_RO_PDS_STATE         PDS_RO_PDS_STATE
#define PDS_RO_PDS_STATE_POS     (0U)
#define PDS_RO_PDS_STATE_LEN     (5U)
#define PDS_RO_PDS_STATE_MSK     (((1U << PDS_RO_PDS_STATE_LEN) - 1) << PDS_RO_PDS_STATE_POS)
#define PDS_RO_PDS_STATE_UMSK    (~(((1U << PDS_RO_PDS_STATE_LEN) - 1) << PDS_RO_PDS_STATE_POS))
#define PDS_RO_PDS_RF_STATE      PDS_RO_PDS_RF_STATE
#define PDS_RO_PDS_RF_STATE_POS  (8U)
#define PDS_RO_PDS_RF_STATE_LEN  (5U)
#define PDS_RO_PDS_RF_STATE_MSK  (((1U << PDS_RO_PDS_RF_STATE_LEN) - 1) << PDS_RO_PDS_RF_STATE_POS)
#define PDS_RO_PDS_RF_STATE_UMSK (~(((1U << PDS_RO_PDS_RF_STATE_LEN) - 1) << PDS_RO_PDS_RF_STATE_POS))
#define PDS_RESET_EVENT          PDS_RESET_EVENT
#define PDS_RESET_EVENT_POS      (24U)
#define PDS_RESET_EVENT_LEN      (3U)
#define PDS_RESET_EVENT_MSK      (((1U << PDS_RESET_EVENT_LEN) - 1) << PDS_RESET_EVENT_POS)
#define PDS_RESET_EVENT_UMSK     (~(((1U << PDS_RESET_EVENT_LEN) - 1) << PDS_RESET_EVENT_POS))
#define PDS_CLR_RESET_EVENT      PDS_CLR_RESET_EVENT
#define PDS_CLR_RESET_EVENT_POS  (31U)
#define PDS_CLR_RESET_EVENT_LEN  (1U)
#define PDS_CLR_RESET_EVENT_MSK  (((1U << PDS_CLR_RESET_EVENT_LEN) - 1) << PDS_CLR_RESET_EVENT_POS)
#define PDS_CLR_RESET_EVENT_UMSK (~(((1U << PDS_CLR_RESET_EVENT_LEN) - 1) << PDS_CLR_RESET_EVENT_POS))

/* 0x20 : pds_ram1 */
#define PDS_RAM1_OFFSET                   (0x20)
#define PDS_CR_PDS_RAM_CLK_CNT            PDS_CR_PDS_RAM_CLK_CNT
#define PDS_CR_PDS_RAM_CLK_CNT_POS        (8U)
#define PDS_CR_PDS_RAM_CLK_CNT_LEN        (6U)
#define PDS_CR_PDS_RAM_CLK_CNT_MSK        (((1U << PDS_CR_PDS_RAM_CLK_CNT_LEN) - 1) << PDS_CR_PDS_RAM_CLK_CNT_POS)
#define PDS_CR_PDS_RAM_CLK_CNT_UMSK       (~(((1U << PDS_CR_PDS_RAM_CLK_CNT_LEN) - 1) << PDS_CR_PDS_RAM_CLK_CNT_POS))
#define PDS_CR_PDS_RAM_CLK2_CNT           PDS_CR_PDS_RAM_CLK2_CNT
#define PDS_CR_PDS_RAM_CLK2_CNT_POS       (16U)
#define PDS_CR_PDS_RAM_CLK2_CNT_LEN       (6U)
#define PDS_CR_PDS_RAM_CLK2_CNT_MSK       (((1U << PDS_CR_PDS_RAM_CLK2_CNT_LEN) - 1) << PDS_CR_PDS_RAM_CLK2_CNT_POS)
#define PDS_CR_PDS_RAM_CLK2_CNT_UMSK      (~(((1U << PDS_CR_PDS_RAM_CLK2_CNT_LEN) - 1) << PDS_CR_PDS_RAM_CLK2_CNT_POS))
#define PDS_CR_PDS_CTRL_NP_RAM_CLK        PDS_CR_PDS_CTRL_NP_RAM_CLK
#define PDS_CR_PDS_CTRL_NP_RAM_CLK_POS    (24U)
#define PDS_CR_PDS_CTRL_NP_RAM_CLK_LEN    (1U)
#define PDS_CR_PDS_CTRL_NP_RAM_CLK_MSK    (((1U << PDS_CR_PDS_CTRL_NP_RAM_CLK_LEN) - 1) << PDS_CR_PDS_CTRL_NP_RAM_CLK_POS)
#define PDS_CR_PDS_CTRL_NP_RAM_CLK_UMSK   (~(((1U << PDS_CR_PDS_CTRL_NP_RAM_CLK_LEN) - 1) << PDS_CR_PDS_CTRL_NP_RAM_CLK_POS))
#define PDS_CR_PDS_CTRL_WB_RAM_CLK        PDS_CR_PDS_CTRL_WB_RAM_CLK
#define PDS_CR_PDS_CTRL_WB_RAM_CLK_POS    (26U)
#define PDS_CR_PDS_CTRL_WB_RAM_CLK_LEN    (1U)
#define PDS_CR_PDS_CTRL_WB_RAM_CLK_MSK    (((1U << PDS_CR_PDS_CTRL_WB_RAM_CLK_LEN) - 1) << PDS_CR_PDS_CTRL_WB_RAM_CLK_POS)
#define PDS_CR_PDS_CTRL_WB_RAM_CLK_UMSK   (~(((1U << PDS_CR_PDS_CTRL_WB_RAM_CLK_LEN) - 1) << PDS_CR_PDS_CTRL_WB_RAM_CLK_POS))
#define PDS_CR_PDS_CTRL_USB_RAM_CLK       PDS_CR_PDS_CTRL_USB_RAM_CLK
#define PDS_CR_PDS_CTRL_USB_RAM_CLK_POS   (27U)
#define PDS_CR_PDS_CTRL_USB_RAM_CLK_LEN   (1U)
#define PDS_CR_PDS_CTRL_USB_RAM_CLK_MSK   (((1U << PDS_CR_PDS_CTRL_USB_RAM_CLK_LEN) - 1) << PDS_CR_PDS_CTRL_USB_RAM_CLK_POS)
#define PDS_CR_PDS_CTRL_USB_RAM_CLK_UMSK  (~(((1U << PDS_CR_PDS_CTRL_USB_RAM_CLK_LEN) - 1) << PDS_CR_PDS_CTRL_USB_RAM_CLK_POS))
#define PDS_CR_PDS_CTRL_MISC_RAM_CLK      PDS_CR_PDS_CTRL_MISC_RAM_CLK
#define PDS_CR_PDS_CTRL_MISC_RAM_CLK_POS  (28U)
#define PDS_CR_PDS_CTRL_MISC_RAM_CLK_LEN  (1U)
#define PDS_CR_PDS_CTRL_MISC_RAM_CLK_MSK  (((1U << PDS_CR_PDS_CTRL_MISC_RAM_CLK_LEN) - 1) << PDS_CR_PDS_CTRL_MISC_RAM_CLK_POS)
#define PDS_CR_PDS_CTRL_MISC_RAM_CLK_UMSK (~(((1U << PDS_CR_PDS_CTRL_MISC_RAM_CLK_LEN) - 1) << PDS_CR_PDS_CTRL_MISC_RAM_CLK_POS))
#define PDS_CR_PDS_CTRL_RAM_CLK2          PDS_CR_PDS_CTRL_RAM_CLK2
#define PDS_CR_PDS_CTRL_RAM_CLK2_POS      (30U)
#define PDS_CR_PDS_CTRL_RAM_CLK2_LEN      (1U)
#define PDS_CR_PDS_CTRL_RAM_CLK2_MSK      (((1U << PDS_CR_PDS_CTRL_RAM_CLK2_LEN) - 1) << PDS_CR_PDS_CTRL_RAM_CLK2_POS)
#define PDS_CR_PDS_CTRL_RAM_CLK2_UMSK     (~(((1U << PDS_CR_PDS_CTRL_RAM_CLK2_LEN) - 1) << PDS_CR_PDS_CTRL_RAM_CLK2_POS))
#define PDS_CR_PDS_CTRL_RAM_CLK           PDS_CR_PDS_CTRL_RAM_CLK
#define PDS_CR_PDS_CTRL_RAM_CLK_POS       (31U)
#define PDS_CR_PDS_CTRL_RAM_CLK_LEN       (1U)
#define PDS_CR_PDS_CTRL_RAM_CLK_MSK       (((1U << PDS_CR_PDS_CTRL_RAM_CLK_LEN) - 1) << PDS_CR_PDS_CTRL_RAM_CLK_POS)
#define PDS_CR_PDS_CTRL_RAM_CLK_UMSK      (~(((1U << PDS_CR_PDS_CTRL_RAM_CLK_LEN) - 1) << PDS_CR_PDS_CTRL_RAM_CLK_POS))

/* 0x24 : PDS_CTL5 */
#define PDS_CTL5_OFFSET              (0x24)
#define PDS_CR_NP_WFI_MASK           PDS_CR_NP_WFI_MASK
#define PDS_CR_NP_WFI_MASK_POS       (0U)
#define PDS_CR_NP_WFI_MASK_LEN       (1U)
#define PDS_CR_NP_WFI_MASK_MSK       (((1U << PDS_CR_NP_WFI_MASK_LEN) - 1) << PDS_CR_NP_WFI_MASK_POS)
#define PDS_CR_NP_WFI_MASK_UMSK      (~(((1U << PDS_CR_NP_WFI_MASK_LEN) - 1) << PDS_CR_NP_WFI_MASK_POS))
#define PDS_CR_PDS_PAD_OD_EN         PDS_CR_PDS_PAD_OD_EN
#define PDS_CR_PDS_PAD_OD_EN_POS     (1U)
#define PDS_CR_PDS_PAD_OD_EN_LEN     (1U)
#define PDS_CR_PDS_PAD_OD_EN_MSK     (((1U << PDS_CR_PDS_PAD_OD_EN_LEN) - 1) << PDS_CR_PDS_PAD_OD_EN_POS)
#define PDS_CR_PDS_PAD_OD_EN_UMSK    (~(((1U << PDS_CR_PDS_PAD_OD_EN_LEN) - 1) << PDS_CR_PDS_PAD_OD_EN_POS))
#define PDS_CR_PDS_CTRL_USB33        PDS_CR_PDS_CTRL_USB33
#define PDS_CR_PDS_CTRL_USB33_POS    (8U)
#define PDS_CR_PDS_CTRL_USB33_LEN    (1U)
#define PDS_CR_PDS_CTRL_USB33_MSK    (((1U << PDS_CR_PDS_CTRL_USB33_LEN) - 1) << PDS_CR_PDS_CTRL_USB33_POS)
#define PDS_CR_PDS_CTRL_USB33_UMSK   (~(((1U << PDS_CR_PDS_CTRL_USB33_LEN) - 1) << PDS_CR_PDS_CTRL_USB33_POS))
#define PDS_CR_PDS_PD_LDO18IO        PDS_CR_PDS_PD_LDO18IO
#define PDS_CR_PDS_PD_LDO18IO_POS    (9U)
#define PDS_CR_PDS_PD_LDO18IO_LEN    (1U)
#define PDS_CR_PDS_PD_LDO18IO_MSK    (((1U << PDS_CR_PDS_PD_LDO18IO_LEN) - 1) << PDS_CR_PDS_PD_LDO18IO_POS)
#define PDS_CR_PDS_PD_LDO18IO_UMSK   (~(((1U << PDS_CR_PDS_PD_LDO18IO_LEN) - 1) << PDS_CR_PDS_PD_LDO18IO_POS))
#define PDS_CR_PDS_GPIO_KEEP_EN      PDS_CR_PDS_GPIO_KEEP_EN
#define PDS_CR_PDS_GPIO_KEEP_EN_POS  (16U)
#define PDS_CR_PDS_GPIO_KEEP_EN_LEN  (3U)
#define PDS_CR_PDS_GPIO_KEEP_EN_MSK  (((1U << PDS_CR_PDS_GPIO_KEEP_EN_LEN) - 1) << PDS_CR_PDS_GPIO_KEEP_EN_POS)
#define PDS_CR_PDS_GPIO_KEEP_EN_UMSK (~(((1U << PDS_CR_PDS_GPIO_KEEP_EN_LEN) - 1) << PDS_CR_PDS_GPIO_KEEP_EN_POS))

/* 0x28 : PDS_RAM2 */
#define PDS_RAM2_OFFSET      (0x28)
#define PDS_CR_WRAM_SLP      PDS_CR_WRAM_SLP
#define PDS_CR_WRAM_SLP_POS  (0U)
#define PDS_CR_WRAM_SLP_LEN  (10U)
#define PDS_CR_WRAM_SLP_MSK  (((1U << PDS_CR_WRAM_SLP_LEN) - 1) << PDS_CR_WRAM_SLP_POS)
#define PDS_CR_WRAM_SLP_UMSK (~(((1U << PDS_CR_WRAM_SLP_LEN) - 1) << PDS_CR_WRAM_SLP_POS))
#define PDS_CR_WRAM_RET      PDS_CR_WRAM_RET
#define PDS_CR_WRAM_RET_POS  (10U)
#define PDS_CR_WRAM_RET_LEN  (10U)
#define PDS_CR_WRAM_RET_MSK  (((1U << PDS_CR_WRAM_RET_LEN) - 1) << PDS_CR_WRAM_RET_POS)
#define PDS_CR_WRAM_RET_UMSK (~(((1U << PDS_CR_WRAM_RET_LEN) - 1) << PDS_CR_WRAM_RET_POS))

/* 0x30 : pds_gpio_i_set */
#define PDS_GPIO_I_SET_OFFSET       (0x30)
#define PDS_CR_PDS_GPIO_IE_SET      PDS_CR_PDS_GPIO_IE_SET
#define PDS_CR_PDS_GPIO_IE_SET_POS  (0U)
#define PDS_CR_PDS_GPIO_IE_SET_LEN  (2U)
#define PDS_CR_PDS_GPIO_IE_SET_MSK  (((1U << PDS_CR_PDS_GPIO_IE_SET_LEN) - 1) << PDS_CR_PDS_GPIO_IE_SET_POS)
#define PDS_CR_PDS_GPIO_IE_SET_UMSK (~(((1U << PDS_CR_PDS_GPIO_IE_SET_LEN) - 1) << PDS_CR_PDS_GPIO_IE_SET_POS))
#define PDS_CR_PDS_GPIO_PD_SET      PDS_CR_PDS_GPIO_PD_SET
#define PDS_CR_PDS_GPIO_PD_SET_POS  (3U)
#define PDS_CR_PDS_GPIO_PD_SET_LEN  (2U)
#define PDS_CR_PDS_GPIO_PD_SET_MSK  (((1U << PDS_CR_PDS_GPIO_PD_SET_LEN) - 1) << PDS_CR_PDS_GPIO_PD_SET_POS)
#define PDS_CR_PDS_GPIO_PD_SET_UMSK (~(((1U << PDS_CR_PDS_GPIO_PD_SET_LEN) - 1) << PDS_CR_PDS_GPIO_PD_SET_POS))
#define PDS_CR_PDS_GPIO_PU_SET      PDS_CR_PDS_GPIO_PU_SET
#define PDS_CR_PDS_GPIO_PU_SET_POS  (6U)
#define PDS_CR_PDS_GPIO_PU_SET_LEN  (2U)
#define PDS_CR_PDS_GPIO_PU_SET_MSK  (((1U << PDS_CR_PDS_GPIO_PU_SET_LEN) - 1) << PDS_CR_PDS_GPIO_PU_SET_POS)
#define PDS_CR_PDS_GPIO_PU_SET_UMSK (~(((1U << PDS_CR_PDS_GPIO_PU_SET_LEN) - 1) << PDS_CR_PDS_GPIO_PU_SET_POS))

/* 0x34 : pds_gpio_pd_set */
#define PDS_GPIO_PD_SET_OFFSET            (0x34)
#define PDS_CR_PDS_GPIO_SET_INT_MASK      PDS_CR_PDS_GPIO_SET_INT_MASK
#define PDS_CR_PDS_GPIO_SET_INT_MASK_POS  (0U)
#define PDS_CR_PDS_GPIO_SET_INT_MASK_LEN  (31U)
#define PDS_CR_PDS_GPIO_SET_INT_MASK_MSK  (((1U << PDS_CR_PDS_GPIO_SET_INT_MASK_LEN) - 1) << PDS_CR_PDS_GPIO_SET_INT_MASK_POS)
#define PDS_CR_PDS_GPIO_SET_INT_MASK_UMSK (~(((1U << PDS_CR_PDS_GPIO_SET_INT_MASK_LEN) - 1) << PDS_CR_PDS_GPIO_SET_INT_MASK_POS))

/* 0x40 : pds_gpio_int */
#define PDS_GPIO_INT_OFFSET         (0x40)
#define PDS_GPIO_SET1_INT_CLR       PDS_GPIO_SET1_INT_CLR
#define PDS_GPIO_SET1_INT_CLR_POS   (2U)
#define PDS_GPIO_SET1_INT_CLR_LEN   (1U)
#define PDS_GPIO_SET1_INT_CLR_MSK   (((1U << PDS_GPIO_SET1_INT_CLR_LEN) - 1) << PDS_GPIO_SET1_INT_CLR_POS)
#define PDS_GPIO_SET1_INT_CLR_UMSK  (~(((1U << PDS_GPIO_SET1_INT_CLR_LEN) - 1) << PDS_GPIO_SET1_INT_CLR_POS))
#define PDS_GPIO_SET1_INT_MODE      PDS_GPIO_SET1_INT_MODE
#define PDS_GPIO_SET1_INT_MODE_POS  (4U)
#define PDS_GPIO_SET1_INT_MODE_LEN  (4U)
#define PDS_GPIO_SET1_INT_MODE_MSK  (((1U << PDS_GPIO_SET1_INT_MODE_LEN) - 1) << PDS_GPIO_SET1_INT_MODE_POS)
#define PDS_GPIO_SET1_INT_MODE_UMSK (~(((1U << PDS_GPIO_SET1_INT_MODE_LEN) - 1) << PDS_GPIO_SET1_INT_MODE_POS))
#define PDS_GPIO_SET2_INT_CLR       PDS_GPIO_SET2_INT_CLR
#define PDS_GPIO_SET2_INT_CLR_POS   (10U)
#define PDS_GPIO_SET2_INT_CLR_LEN   (1U)
#define PDS_GPIO_SET2_INT_CLR_MSK   (((1U << PDS_GPIO_SET2_INT_CLR_LEN) - 1) << PDS_GPIO_SET2_INT_CLR_POS)
#define PDS_GPIO_SET2_INT_CLR_UMSK  (~(((1U << PDS_GPIO_SET2_INT_CLR_LEN) - 1) << PDS_GPIO_SET2_INT_CLR_POS))
#define PDS_GPIO_SET2_INT_MODE      PDS_GPIO_SET2_INT_MODE
#define PDS_GPIO_SET2_INT_MODE_POS  (12U)
#define PDS_GPIO_SET2_INT_MODE_LEN  (4U)
#define PDS_GPIO_SET2_INT_MODE_MSK  (((1U << PDS_GPIO_SET2_INT_MODE_LEN) - 1) << PDS_GPIO_SET2_INT_MODE_POS)
#define PDS_GPIO_SET2_INT_MODE_UMSK (~(((1U << PDS_GPIO_SET2_INT_MODE_LEN) - 1) << PDS_GPIO_SET2_INT_MODE_POS))
#define PDS_GPIO_SET3_INT_CLR       PDS_GPIO_SET3_INT_CLR
#define PDS_GPIO_SET3_INT_CLR_POS   (18U)
#define PDS_GPIO_SET3_INT_CLR_LEN   (1U)
#define PDS_GPIO_SET3_INT_CLR_MSK   (((1U << PDS_GPIO_SET3_INT_CLR_LEN) - 1) << PDS_GPIO_SET3_INT_CLR_POS)
#define PDS_GPIO_SET3_INT_CLR_UMSK  (~(((1U << PDS_GPIO_SET3_INT_CLR_LEN) - 1) << PDS_GPIO_SET3_INT_CLR_POS))
#define PDS_GPIO_SET3_INT_MODE      PDS_GPIO_SET3_INT_MODE
#define PDS_GPIO_SET3_INT_MODE_POS  (20U)
#define PDS_GPIO_SET3_INT_MODE_LEN  (4U)
#define PDS_GPIO_SET3_INT_MODE_MSK  (((1U << PDS_GPIO_SET3_INT_MODE_LEN) - 1) << PDS_GPIO_SET3_INT_MODE_POS)
#define PDS_GPIO_SET3_INT_MODE_UMSK (~(((1U << PDS_GPIO_SET3_INT_MODE_LEN) - 1) << PDS_GPIO_SET3_INT_MODE_POS))
#define PDS_GPIO_SET4_INT_CLR       PDS_GPIO_SET4_INT_CLR
#define PDS_GPIO_SET4_INT_CLR_POS   (26U)
#define PDS_GPIO_SET4_INT_CLR_LEN   (1U)
#define PDS_GPIO_SET4_INT_CLR_MSK   (((1U << PDS_GPIO_SET4_INT_CLR_LEN) - 1) << PDS_GPIO_SET4_INT_CLR_POS)
#define PDS_GPIO_SET4_INT_CLR_UMSK  (~(((1U << PDS_GPIO_SET4_INT_CLR_LEN) - 1) << PDS_GPIO_SET4_INT_CLR_POS))
#define PDS_GPIO_SET4_INT_MODE      PDS_GPIO_SET4_INT_MODE
#define PDS_GPIO_SET4_INT_MODE_POS  (28U)
#define PDS_GPIO_SET4_INT_MODE_LEN  (4U)
#define PDS_GPIO_SET4_INT_MODE_MSK  (((1U << PDS_GPIO_SET4_INT_MODE_LEN) - 1) << PDS_GPIO_SET4_INT_MODE_POS)
#define PDS_GPIO_SET4_INT_MODE_UMSK (~(((1U << PDS_GPIO_SET4_INT_MODE_LEN) - 1) << PDS_GPIO_SET4_INT_MODE_POS))

/* 0x44 : pds_gpio_stat */
#define PDS_GPIO_STAT_OFFSET   (0x44)
#define PDS_GPIO_INT_STAT      PDS_GPIO_INT_STAT
#define PDS_GPIO_INT_STAT_POS  (0U)
#define PDS_GPIO_INT_STAT_LEN  (31U)
#define PDS_GPIO_INT_STAT_MSK  (((1U << PDS_GPIO_INT_STAT_LEN) - 1) << PDS_GPIO_INT_STAT_POS)
#define PDS_GPIO_INT_STAT_UMSK (~(((1U << PDS_GPIO_INT_STAT_LEN) - 1) << PDS_GPIO_INT_STAT_POS))

/* 0x48 : PDS_RAM3 */
#define PDS_RAM3_OFFSET       (0x48)
#define PDS_CR_OCRAM_RET      PDS_CR_OCRAM_RET
#define PDS_CR_OCRAM_RET_POS  (0U)
#define PDS_CR_OCRAM_RET_LEN  (20U)
#define PDS_CR_OCRAM_RET_MSK  (((1U << PDS_CR_OCRAM_RET_LEN) - 1) << PDS_CR_OCRAM_RET_POS)
#define PDS_CR_OCRAM_RET_UMSK (~(((1U << PDS_CR_OCRAM_RET_LEN) - 1) << PDS_CR_OCRAM_RET_POS))

/* 0x4C : PDS_RAM4 */
#define PDS_RAM4_OFFSET       (0x4C)
#define PDS_CR_OCRAM_SLP      PDS_CR_OCRAM_SLP
#define PDS_CR_OCRAM_SLP_POS  (0U)
#define PDS_CR_OCRAM_SLP_LEN  (20U)
#define PDS_CR_OCRAM_SLP_MSK  (((1U << PDS_CR_OCRAM_SLP_LEN) - 1) << PDS_CR_OCRAM_SLP_POS)
#define PDS_CR_OCRAM_SLP_UMSK (~(((1U << PDS_CR_OCRAM_SLP_LEN) - 1) << PDS_CR_OCRAM_SLP_POS))

/* 0x114 : cpu_core_cfg1 */
#define PDS_CPU_CORE_CFG1_OFFSET (0x114)
#define PDS_REG_PLL_SEL          PDS_REG_PLL_SEL
#define PDS_REG_PLL_SEL_POS      (4U)
#define PDS_REG_PLL_SEL_LEN      (2U)
#define PDS_REG_PLL_SEL_MSK      (((1U << PDS_REG_PLL_SEL_LEN) - 1) << PDS_REG_PLL_SEL_POS)
#define PDS_REG_PLL_SEL_UMSK     (~(((1U << PDS_REG_PLL_SEL_LEN) - 1) << PDS_REG_PLL_SEL_POS))
#define PDS_REG_MCU1_CLK_EN      PDS_REG_MCU1_CLK_EN
#define PDS_REG_MCU1_CLK_EN_POS  (8U)
#define PDS_REG_MCU1_CLK_EN_LEN  (1U)
#define PDS_REG_MCU1_CLK_EN_MSK  (((1U << PDS_REG_MCU1_CLK_EN_LEN) - 1) << PDS_REG_MCU1_CLK_EN_POS)
#define PDS_REG_MCU1_CLK_EN_UMSK (~(((1U << PDS_REG_MCU1_CLK_EN_LEN) - 1) << PDS_REG_MCU1_CLK_EN_POS))

/* 0x148 : cpu_core_cfg14 */
#define PDS_CPU_CORE_CFG14_OFFSET (0x148)
#define PDS_E906_RST_ADDR         PDS_E906_RST_ADDR
#define PDS_E906_RST_ADDR_POS     (0U)
#define PDS_E906_RST_ADDR_LEN     (32U)
#define PDS_E906_RST_ADDR_MSK     (((1U << PDS_E906_RST_ADDR_LEN) - 1) << PDS_E906_RST_ADDR_POS)
#define PDS_E906_RST_ADDR_UMSK    (~(((1U << PDS_E906_RST_ADDR_LEN) - 1) << PDS_E906_RST_ADDR_POS))

/* 0x300 : rc32m_ctrl0 */
#define PDS_RC32M_CTRL0_OFFSET         (0x300)
#define PDS_RC32M_CAL_DONE             PDS_RC32M_CAL_DONE
#define PDS_RC32M_CAL_DONE_POS         (0U)
#define PDS_RC32M_CAL_DONE_LEN         (1U)
#define PDS_RC32M_CAL_DONE_MSK         (((1U << PDS_RC32M_CAL_DONE_LEN) - 1) << PDS_RC32M_CAL_DONE_POS)
#define PDS_RC32M_CAL_DONE_UMSK        (~(((1U << PDS_RC32M_CAL_DONE_LEN) - 1) << PDS_RC32M_CAL_DONE_POS))
#define PDS_RC32M_RDY                  PDS_RC32M_RDY
#define PDS_RC32M_RDY_POS              (1U)
#define PDS_RC32M_RDY_LEN              (1U)
#define PDS_RC32M_RDY_MSK              (((1U << PDS_RC32M_RDY_LEN) - 1) << PDS_RC32M_RDY_POS)
#define PDS_RC32M_RDY_UMSK             (~(((1U << PDS_RC32M_RDY_LEN) - 1) << PDS_RC32M_RDY_POS))
#define PDS_RC32M_CAL_INPROGRESS       PDS_RC32M_CAL_INPROGRESS
#define PDS_RC32M_CAL_INPROGRESS_POS   (2U)
#define PDS_RC32M_CAL_INPROGRESS_LEN   (1U)
#define PDS_RC32M_CAL_INPROGRESS_MSK   (((1U << PDS_RC32M_CAL_INPROGRESS_LEN) - 1) << PDS_RC32M_CAL_INPROGRESS_POS)
#define PDS_RC32M_CAL_INPROGRESS_UMSK  (~(((1U << PDS_RC32M_CAL_INPROGRESS_LEN) - 1) << PDS_RC32M_CAL_INPROGRESS_POS))
#define PDS_RC32M_CAL_DIV              PDS_RC32M_CAL_DIV
#define PDS_RC32M_CAL_DIV_POS          (3U)
#define PDS_RC32M_CAL_DIV_LEN          (2U)
#define PDS_RC32M_CAL_DIV_MSK          (((1U << PDS_RC32M_CAL_DIV_LEN) - 1) << PDS_RC32M_CAL_DIV_POS)
#define PDS_RC32M_CAL_DIV_UMSK         (~(((1U << PDS_RC32M_CAL_DIV_LEN) - 1) << PDS_RC32M_CAL_DIV_POS))
#define PDS_RC32M_CAL_PRECHARGE        PDS_RC32M_CAL_PRECHARGE
#define PDS_RC32M_CAL_PRECHARGE_POS    (5U)
#define PDS_RC32M_CAL_PRECHARGE_LEN    (1U)
#define PDS_RC32M_CAL_PRECHARGE_MSK    (((1U << PDS_RC32M_CAL_PRECHARGE_LEN) - 1) << PDS_RC32M_CAL_PRECHARGE_POS)
#define PDS_RC32M_CAL_PRECHARGE_UMSK   (~(((1U << PDS_RC32M_CAL_PRECHARGE_LEN) - 1) << PDS_RC32M_CAL_PRECHARGE_POS))
#define PDS_RC32M_DIG_CODE_FR_CAL      PDS_RC32M_DIG_CODE_FR_CAL
#define PDS_RC32M_DIG_CODE_FR_CAL_POS  (6U)
#define PDS_RC32M_DIG_CODE_FR_CAL_LEN  (8U)
#define PDS_RC32M_DIG_CODE_FR_CAL_MSK  (((1U << PDS_RC32M_DIG_CODE_FR_CAL_LEN) - 1) << PDS_RC32M_DIG_CODE_FR_CAL_POS)
#define PDS_RC32M_DIG_CODE_FR_CAL_UMSK (~(((1U << PDS_RC32M_DIG_CODE_FR_CAL_LEN) - 1) << PDS_RC32M_DIG_CODE_FR_CAL_POS))
#define PDS_RC32M_ALLOW_CAL            PDS_RC32M_ALLOW_CAL
#define PDS_RC32M_ALLOW_CAL_POS        (17U)
#define PDS_RC32M_ALLOW_CAL_LEN        (1U)
#define PDS_RC32M_ALLOW_CAL_MSK        (((1U << PDS_RC32M_ALLOW_CAL_LEN) - 1) << PDS_RC32M_ALLOW_CAL_POS)
#define PDS_RC32M_ALLOW_CAL_UMSK       (~(((1U << PDS_RC32M_ALLOW_CAL_LEN) - 1) << PDS_RC32M_ALLOW_CAL_POS))
#define PDS_RC32M_REFCLK_HALF          PDS_RC32M_REFCLK_HALF
#define PDS_RC32M_REFCLK_HALF_POS      (18U)
#define PDS_RC32M_REFCLK_HALF_LEN      (1U)
#define PDS_RC32M_REFCLK_HALF_MSK      (((1U << PDS_RC32M_REFCLK_HALF_LEN) - 1) << PDS_RC32M_REFCLK_HALF_POS)
#define PDS_RC32M_REFCLK_HALF_UMSK     (~(((1U << PDS_RC32M_REFCLK_HALF_LEN) - 1) << PDS_RC32M_REFCLK_HALF_POS))
#define PDS_RC32M_EXT_CODE_EN          PDS_RC32M_EXT_CODE_EN
#define PDS_RC32M_EXT_CODE_EN_POS      (19U)
#define PDS_RC32M_EXT_CODE_EN_LEN      (1U)
#define PDS_RC32M_EXT_CODE_EN_MSK      (((1U << PDS_RC32M_EXT_CODE_EN_LEN) - 1) << PDS_RC32M_EXT_CODE_EN_POS)
#define PDS_RC32M_EXT_CODE_EN_UMSK     (~(((1U << PDS_RC32M_EXT_CODE_EN_LEN) - 1) << PDS_RC32M_EXT_CODE_EN_POS))
#define PDS_RC32M_CAL_EN               PDS_RC32M_CAL_EN
#define PDS_RC32M_CAL_EN_POS           (20U)
#define PDS_RC32M_CAL_EN_LEN           (1U)
#define PDS_RC32M_CAL_EN_MSK           (((1U << PDS_RC32M_CAL_EN_LEN) - 1) << PDS_RC32M_CAL_EN_POS)
#define PDS_RC32M_CAL_EN_UMSK          (~(((1U << PDS_RC32M_CAL_EN_LEN) - 1) << PDS_RC32M_CAL_EN_POS))
#define PDS_RC32M_PD                   PDS_RC32M_PD
#define PDS_RC32M_PD_POS               (21U)
#define PDS_RC32M_PD_LEN               (1U)
#define PDS_RC32M_PD_MSK               (((1U << PDS_RC32M_PD_LEN) - 1) << PDS_RC32M_PD_POS)
#define PDS_RC32M_PD_UMSK              (~(((1U << PDS_RC32M_PD_LEN) - 1) << PDS_RC32M_PD_POS))
#define PDS_RC32M_CODE_FR_EXT          PDS_RC32M_CODE_FR_EXT
#define PDS_RC32M_CODE_FR_EXT_POS      (22U)
#define PDS_RC32M_CODE_FR_EXT_LEN      (8U)
#define PDS_RC32M_CODE_FR_EXT_MSK      (((1U << PDS_RC32M_CODE_FR_EXT_LEN) - 1) << PDS_RC32M_CODE_FR_EXT_POS)
#define PDS_RC32M_CODE_FR_EXT_UMSK     (~(((1U << PDS_RC32M_CODE_FR_EXT_LEN) - 1) << PDS_RC32M_CODE_FR_EXT_POS))

/* 0x304 : rc32m_ctrl1 */
#define PDS_RC32M_CTRL1_OFFSET      (0x304)
#define PDS_RC32M_TEST_EN           PDS_RC32M_TEST_EN
#define PDS_RC32M_TEST_EN_POS       (0U)
#define PDS_RC32M_TEST_EN_LEN       (1U)
#define PDS_RC32M_TEST_EN_MSK       (((1U << PDS_RC32M_TEST_EN_LEN) - 1) << PDS_RC32M_TEST_EN_POS)
#define PDS_RC32M_TEST_EN_UMSK      (~(((1U << PDS_RC32M_TEST_EN_LEN) - 1) << PDS_RC32M_TEST_EN_POS))
#define PDS_RC32M_SOFT_RST          PDS_RC32M_SOFT_RST
#define PDS_RC32M_SOFT_RST_POS      (1U)
#define PDS_RC32M_SOFT_RST_LEN      (1U)
#define PDS_RC32M_SOFT_RST_MSK      (((1U << PDS_RC32M_SOFT_RST_LEN) - 1) << PDS_RC32M_SOFT_RST_POS)
#define PDS_RC32M_SOFT_RST_UMSK     (~(((1U << PDS_RC32M_SOFT_RST_LEN) - 1) << PDS_RC32M_SOFT_RST_POS))
#define PDS_RC32M_CLK_SOFT_RST      PDS_RC32M_CLK_SOFT_RST
#define PDS_RC32M_CLK_SOFT_RST_POS  (2U)
#define PDS_RC32M_CLK_SOFT_RST_LEN  (1U)
#define PDS_RC32M_CLK_SOFT_RST_MSK  (((1U << PDS_RC32M_CLK_SOFT_RST_LEN) - 1) << PDS_RC32M_CLK_SOFT_RST_POS)
#define PDS_RC32M_CLK_SOFT_RST_UMSK (~(((1U << PDS_RC32M_CLK_SOFT_RST_LEN) - 1) << PDS_RC32M_CLK_SOFT_RST_POS))
#define PDS_RC32M_CLK_INV           PDS_RC32M_CLK_INV
#define PDS_RC32M_CLK_INV_POS       (3U)
#define PDS_RC32M_CLK_INV_LEN       (1U)
#define PDS_RC32M_CLK_INV_MSK       (((1U << PDS_RC32M_CLK_INV_LEN) - 1) << PDS_RC32M_CLK_INV_POS)
#define PDS_RC32M_CLK_INV_UMSK      (~(((1U << PDS_RC32M_CLK_INV_LEN) - 1) << PDS_RC32M_CLK_INV_POS))
#define PDS_RC32M_CLK_FORCE_ON      PDS_RC32M_CLK_FORCE_ON
#define PDS_RC32M_CLK_FORCE_ON_POS  (4U)
#define PDS_RC32M_CLK_FORCE_ON_LEN  (1U)
#define PDS_RC32M_CLK_FORCE_ON_MSK  (((1U << PDS_RC32M_CLK_FORCE_ON_LEN) - 1) << PDS_RC32M_CLK_FORCE_ON_POS)
#define PDS_RC32M_CLK_FORCE_ON_UMSK (~(((1U << PDS_RC32M_CLK_FORCE_ON_LEN) - 1) << PDS_RC32M_CLK_FORCE_ON_POS))
#define PDS_RC32M_RESERVED          PDS_RC32M_RESERVED
#define PDS_RC32M_RESERVED_POS      (24U)
#define PDS_RC32M_RESERVED_LEN      (8U)
#define PDS_RC32M_RESERVED_MSK      (((1U << PDS_RC32M_RESERVED_LEN) - 1) << PDS_RC32M_RESERVED_POS)
#define PDS_RC32M_RESERVED_UMSK     (~(((1U << PDS_RC32M_RESERVED_LEN) - 1) << PDS_RC32M_RESERVED_POS))

/* 0x308 : rc32m_ctrl2 */
#define PDS_RC32M_CTRL2_OFFSET      (0x308)
#define PDS_RC32M_CODE_FR_EXT2      PDS_RC32M_CODE_FR_EXT2
#define PDS_RC32M_CODE_FR_EXT2_POS  (22U)
#define PDS_RC32M_CODE_FR_EXT2_LEN  (8U)
#define PDS_RC32M_CODE_FR_EXT2_MSK  (((1U << PDS_RC32M_CODE_FR_EXT2_LEN) - 1) << PDS_RC32M_CODE_FR_EXT2_POS)
#define PDS_RC32M_CODE_FR_EXT2_UMSK (~(((1U << PDS_RC32M_CODE_FR_EXT2_LEN) - 1) << PDS_RC32M_CODE_FR_EXT2_POS))
#define PDS_RC32M_EXT_CODE_SEL      PDS_RC32M_EXT_CODE_SEL
#define PDS_RC32M_EXT_CODE_SEL_POS  (31U)
#define PDS_RC32M_EXT_CODE_SEL_LEN  (1U)
#define PDS_RC32M_EXT_CODE_SEL_MSK  (((1U << PDS_RC32M_EXT_CODE_SEL_LEN) - 1) << PDS_RC32M_EXT_CODE_SEL_POS)
#define PDS_RC32M_EXT_CODE_SEL_UMSK (~(((1U << PDS_RC32M_EXT_CODE_SEL_LEN) - 1) << PDS_RC32M_EXT_CODE_SEL_POS))

/* 0x400 : pu_rst_clkpll */
#define PDS_PU_RST_CLKPLL_OFFSET        (0x400)
#define PDS_CR_PDS_PU_CLKPLL_SFREG      PDS_CR_PDS_PU_CLKPLL_SFREG
#define PDS_CR_PDS_PU_CLKPLL_SFREG_POS  (9U)
#define PDS_CR_PDS_PU_CLKPLL_SFREG_LEN  (1U)
#define PDS_CR_PDS_PU_CLKPLL_SFREG_MSK  (((1U << PDS_CR_PDS_PU_CLKPLL_SFREG_LEN) - 1) << PDS_CR_PDS_PU_CLKPLL_SFREG_POS)
#define PDS_CR_PDS_PU_CLKPLL_SFREG_UMSK (~(((1U << PDS_CR_PDS_PU_CLKPLL_SFREG_LEN) - 1) << PDS_CR_PDS_PU_CLKPLL_SFREG_POS))
#define PDS_CR_PDS_PU_CLKPLL            PDS_CR_PDS_PU_CLKPLL
#define PDS_CR_PDS_PU_CLKPLL_POS        (10U)
#define PDS_CR_PDS_PU_CLKPLL_LEN        (1U)
#define PDS_CR_PDS_PU_CLKPLL_MSK        (((1U << PDS_CR_PDS_PU_CLKPLL_LEN) - 1) << PDS_CR_PDS_PU_CLKPLL_POS)
#define PDS_CR_PDS_PU_CLKPLL_UMSK       (~(((1U << PDS_CR_PDS_PU_CLKPLL_LEN) - 1) << PDS_CR_PDS_PU_CLKPLL_POS))

/* 0x500 : usb_ctl */
#define PDS_USB_CTL_OFFSET          (0x500)
#define PDS_REG_USB_SW_RST_N        PDS_REG_USB_SW_RST_N
#define PDS_REG_USB_SW_RST_N_POS    (0U)
#define PDS_REG_USB_SW_RST_N_LEN    (1U)
#define PDS_REG_USB_SW_RST_N_MSK    (((1U << PDS_REG_USB_SW_RST_N_LEN) - 1) << PDS_REG_USB_SW_RST_N_POS)
#define PDS_REG_USB_SW_RST_N_UMSK   (~(((1U << PDS_REG_USB_SW_RST_N_LEN) - 1) << PDS_REG_USB_SW_RST_N_POS))
#define PDS_REG_USB_EXT_SUSP_N      PDS_REG_USB_EXT_SUSP_N
#define PDS_REG_USB_EXT_SUSP_N_POS  (1U)
#define PDS_REG_USB_EXT_SUSP_N_LEN  (1U)
#define PDS_REG_USB_EXT_SUSP_N_MSK  (((1U << PDS_REG_USB_EXT_SUSP_N_LEN) - 1) << PDS_REG_USB_EXT_SUSP_N_POS)
#define PDS_REG_USB_EXT_SUSP_N_UMSK (~(((1U << PDS_REG_USB_EXT_SUSP_N_LEN) - 1) << PDS_REG_USB_EXT_SUSP_N_POS))
#define PDS_REG_USB_WAKEUP          PDS_REG_USB_WAKEUP
#define PDS_REG_USB_WAKEUP_POS      (2U)
#define PDS_REG_USB_WAKEUP_LEN      (1U)
#define PDS_REG_USB_WAKEUP_MSK      (((1U << PDS_REG_USB_WAKEUP_LEN) - 1) << PDS_REG_USB_WAKEUP_POS)
#define PDS_REG_USB_WAKEUP_UMSK     (~(((1U << PDS_REG_USB_WAKEUP_LEN) - 1) << PDS_REG_USB_WAKEUP_POS))
#define PDS_REG_USB_L1_WAKEUP       PDS_REG_USB_L1_WAKEUP
#define PDS_REG_USB_L1_WAKEUP_POS   (3U)
#define PDS_REG_USB_L1_WAKEUP_LEN   (1U)
#define PDS_REG_USB_L1_WAKEUP_MSK   (((1U << PDS_REG_USB_L1_WAKEUP_LEN) - 1) << PDS_REG_USB_L1_WAKEUP_POS)
#define PDS_REG_USB_L1_WAKEUP_UMSK  (~(((1U << PDS_REG_USB_L1_WAKEUP_LEN) - 1) << PDS_REG_USB_L1_WAKEUP_POS))
#define PDS_REG_USB_DRVBUS_POL      PDS_REG_USB_DRVBUS_POL
#define PDS_REG_USB_DRVBUS_POL_POS  (4U)
#define PDS_REG_USB_DRVBUS_POL_LEN  (1U)
#define PDS_REG_USB_DRVBUS_POL_MSK  (((1U << PDS_REG_USB_DRVBUS_POL_LEN) - 1) << PDS_REG_USB_DRVBUS_POL_POS)
#define PDS_REG_USB_DRVBUS_POL_UMSK (~(((1U << PDS_REG_USB_DRVBUS_POL_LEN) - 1) << PDS_REG_USB_DRVBUS_POL_POS))
#define PDS_REG_USB_IDDIG           PDS_REG_USB_IDDIG
#define PDS_REG_USB_IDDIG_POS       (5U)
#define PDS_REG_USB_IDDIG_LEN       (1U)
#define PDS_REG_USB_IDDIG_MSK       (((1U << PDS_REG_USB_IDDIG_LEN) - 1) << PDS_REG_USB_IDDIG_POS)
#define PDS_REG_USB_IDDIG_UMSK      (~(((1U << PDS_REG_USB_IDDIG_LEN) - 1) << PDS_REG_USB_IDDIG_POS))

/* 0x504 : usb_phy_ctrl */
#define PDS_USB_PHY_CTRL_OFFSET        (0x504)
#define PDS_REG_USB_PHY_PONRST         PDS_REG_USB_PHY_PONRST
#define PDS_REG_USB_PHY_PONRST_POS     (0U)
#define PDS_REG_USB_PHY_PONRST_LEN     (1U)
#define PDS_REG_USB_PHY_PONRST_MSK     (((1U << PDS_REG_USB_PHY_PONRST_LEN) - 1) << PDS_REG_USB_PHY_PONRST_POS)
#define PDS_REG_USB_PHY_PONRST_UMSK    (~(((1U << PDS_REG_USB_PHY_PONRST_LEN) - 1) << PDS_REG_USB_PHY_PONRST_POS))
#define PDS_REG_USB_PHY_OSCOUTEN       PDS_REG_USB_PHY_OSCOUTEN
#define PDS_REG_USB_PHY_OSCOUTEN_POS   (1U)
#define PDS_REG_USB_PHY_OSCOUTEN_LEN   (1U)
#define PDS_REG_USB_PHY_OSCOUTEN_MSK   (((1U << PDS_REG_USB_PHY_OSCOUTEN_LEN) - 1) << PDS_REG_USB_PHY_OSCOUTEN_POS)
#define PDS_REG_USB_PHY_OSCOUTEN_UMSK  (~(((1U << PDS_REG_USB_PHY_OSCOUTEN_LEN) - 1) << PDS_REG_USB_PHY_OSCOUTEN_POS))
#define PDS_REG_USB_PHY_XTLSEL         PDS_REG_USB_PHY_XTLSEL
#define PDS_REG_USB_PHY_XTLSEL_POS     (2U)
#define PDS_REG_USB_PHY_XTLSEL_LEN     (2U)
#define PDS_REG_USB_PHY_XTLSEL_MSK     (((1U << PDS_REG_USB_PHY_XTLSEL_LEN) - 1) << PDS_REG_USB_PHY_XTLSEL_POS)
#define PDS_REG_USB_PHY_XTLSEL_UMSK    (~(((1U << PDS_REG_USB_PHY_XTLSEL_LEN) - 1) << PDS_REG_USB_PHY_XTLSEL_POS))
#define PDS_REG_USB_PHY_OUTCLKSEL      PDS_REG_USB_PHY_OUTCLKSEL
#define PDS_REG_USB_PHY_OUTCLKSEL_POS  (4U)
#define PDS_REG_USB_PHY_OUTCLKSEL_LEN  (1U)
#define PDS_REG_USB_PHY_OUTCLKSEL_MSK  (((1U << PDS_REG_USB_PHY_OUTCLKSEL_LEN) - 1) << PDS_REG_USB_PHY_OUTCLKSEL_POS)
#define PDS_REG_USB_PHY_OUTCLKSEL_UMSK (~(((1U << PDS_REG_USB_PHY_OUTCLKSEL_LEN) - 1) << PDS_REG_USB_PHY_OUTCLKSEL_POS))
#define PDS_REG_USB_PHY_PLLALIV        PDS_REG_USB_PHY_PLLALIV
#define PDS_REG_USB_PHY_PLLALIV_POS    (5U)
#define PDS_REG_USB_PHY_PLLALIV_LEN    (1U)
#define PDS_REG_USB_PHY_PLLALIV_MSK    (((1U << PDS_REG_USB_PHY_PLLALIV_LEN) - 1) << PDS_REG_USB_PHY_PLLALIV_POS)
#define PDS_REG_USB_PHY_PLLALIV_UMSK   (~(((1U << PDS_REG_USB_PHY_PLLALIV_LEN) - 1) << PDS_REG_USB_PHY_PLLALIV_POS))
#define PDS_REG_PU_USB20_PSW           PDS_REG_PU_USB20_PSW
#define PDS_REG_PU_USB20_PSW_POS       (6U)
#define PDS_REG_PU_USB20_PSW_LEN       (1U)
#define PDS_REG_PU_USB20_PSW_MSK       (((1U << PDS_REG_PU_USB20_PSW_LEN) - 1) << PDS_REG_PU_USB20_PSW_POS)
#define PDS_REG_PU_USB20_PSW_UMSK      (~(((1U << PDS_REG_PU_USB20_PSW_LEN) - 1) << PDS_REG_PU_USB20_PSW_POS))

struct pds_reg {
    /* 0x0 : PDS_CTL */
    union {
        struct {
            uint32_t pds_start_ps                 : 1; /* [    0],        w1p,        0x0 */
            uint32_t cr_sleep_forever             : 1; /* [    1],        r/w,        0x0 */
            uint32_t cr_xtal_force_off            : 1; /* [    2],        r/w,        0x0 */
            uint32_t cr_pds_wifi_save_state       : 1; /* [    3],        r/w,        0x0 */
            uint32_t cr_pds_pd_ldo11              : 1; /* [    4],        r/w,        0x0 */
            uint32_t cr_pds_pd_bg_sys             : 1; /* [    5],        r/w,        0x0 */
            uint32_t cr_pds_ctrl_gpio_ie_pu_pd    : 1; /* [    6],        r/w,        0x0 */
            uint32_t cr_pds_pd_dcdc18             : 1; /* [    7],        r/w,        0x0 */
            uint32_t cr_pds_gate_clk              : 1; /* [    8],        r/w,        0x1 */
            uint32_t cr_pds_mem_stby              : 1; /* [    9],        r/w,        0x1 */
            uint32_t cr_pds_glb_reg_reset_protect : 1; /* [   10],        r/w,        0x0 */
            uint32_t cr_pds_iso_en                : 1; /* [   11],        r/w,        0x1 */
            uint32_t cr_pds_wait_xtal_rdy         : 1; /* [   12],        r/w,        0x0 */
            uint32_t cr_pds_pwr_off               : 1; /* [   13],        r/w,        0x1 */
            uint32_t cr_pds_pd_xtal               : 1; /* [   14],        r/w,        0x1 */
            uint32_t cr_pds_ctrl_soc_enb          : 1; /* [   15],        r/w,        0x0 */
            uint32_t cr_pds_rst_soc               : 1; /* [   16],        r/w,        0x0 */
            uint32_t cr_pds_rc32m_off_dis         : 1; /* [   17],        r/w,        0x0 */
            uint32_t cr_pds_ldo11_vsel_en         : 1; /* [   18],        r/w,        0x0 */
            uint32_t cr_pds_ctrl_usbpll_pd        : 1; /* [   19],        r/w,        0x0 */
            uint32_t cr_pds_ctrl_aupll_pd         : 1; /* [   20],        r/w,        0x0 */
            uint32_t reserved_21                  : 1; /* [   21],       rsvd,        0x0 */
            uint32_t cr_pds_ctrl_wifipll_pd       : 1; /* [   22],        r/w,        0x0 */
            uint32_t cr_pds_ldo11_vol             : 5; /* [27:23],        r/w,        0x8 */
            uint32_t cr_pds_ctrl_rf               : 2; /* [29:28],        r/w,        0x1 */
            uint32_t cr_pds_start_use_tbtt_sleep  : 1; /* [   30],        r/w,        0x0 */
            uint32_t cr_pds_gpio_iso_mode         : 1; /* [   31],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } PDS_CTL;

    /* 0x4 : PDS_TIME1 */
    union {
        struct {
            uint32_t cr_sleep_duration : 32; /* [31: 0],        r/w,      0xca8 */
        } BF;
        uint32_t WORD;
    } PDS_TIME1;

    /* 0x8  reserved */
    uint8_t RESERVED0x8[4];

    /* 0xC : PDS_INT */
    union {
        struct {
            uint32_t ro_pds_wake_int                  : 1;  /* [    0],          r,        0x0 */
            uint32_t ro_pds_rf_done_int               : 1;  /* [    1],          r,        0x0 */
            uint32_t ro_pds_wifi_tbtt_sleep_irq       : 1;  /* [    2],          r,        0x0 */
            uint32_t ro_pds_wifi_tbtt_wakeup_irq      : 1;  /* [    3],          r,        0x0 */
            uint32_t cr_pds_wake_int_mask             : 1;  /* [    4],        r/w,        0x0 */
            uint32_t cr_pds_rf_done_int_mask          : 1;  /* [    5],        r/w,        0x0 */
            uint32_t cr_pds_wifi_tbtt_sleep_irq_mask  : 1;  /* [    6],        r/w,        0x0 */
            uint32_t cr_pds_wifi_tbtt_wakeup_irq_mask : 1;  /* [    7],        r/w,        0x0 */
            uint32_t cr_pds_int_clr                   : 1;  /* [    8],        r/w,        0x0 */
            uint32_t reserved_9                       : 1;  /* [    9],       rsvd,        0x0 */
            uint32_t cr_pds_wakeup_src_en             : 10; /* [19:10],        r/w,      0x3ff */
            uint32_t reserved_20                      : 1;  /* [   20],       rsvd,        0x0 */
            uint32_t ro_pds_wakeup_event              : 10; /* [30:21],          r,        0x0 */
            uint32_t reserved_31                      : 1;  /* [   31],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } PDS_INT;

    /* 0x10 : PDS_CTL2 */
    union {
        struct {
            uint32_t cr_pds_force_np_pwr_off   : 1;  /* [    0],        r/w,        0x0 */
            uint32_t reserved_1                : 1;  /* [    1],       rsvd,        0x0 */
            uint32_t cr_pds_force_wb_pwr_off   : 1;  /* [    2],        r/w,        0x0 */
            uint32_t cr_pds_force_usb_pwr_off  : 1;  /* [    3],        r/w,        0x0 */
            uint32_t cr_pds_force_np_iso_en    : 1;  /* [    4],        r/w,        0x0 */
            uint32_t reserved_5                : 1;  /* [    5],       rsvd,        0x0 */
            uint32_t cr_pds_force_wb_iso_en    : 1;  /* [    6],        r/w,        0x0 */
            uint32_t cr_pds_force_usb_iso_en   : 1;  /* [    7],        r/w,        0x0 */
            uint32_t cr_pds_force_np_pds_rst   : 1;  /* [    8],        r/w,        0x0 */
            uint32_t reserved_9                : 1;  /* [    9],       rsvd,        0x0 */
            uint32_t cr_pds_force_wb_pds_rst   : 1;  /* [   10],        r/w,        0x0 */
            uint32_t cr_pds_force_usb_pds_rst  : 1;  /* [   11],        r/w,        0x0 */
            uint32_t cr_pds_force_np_mem_stby  : 1;  /* [   12],        r/w,        0x0 */
            uint32_t reserved_13               : 1;  /* [   13],       rsvd,        0x0 */
            uint32_t cr_pds_force_wb_mem_stby  : 1;  /* [   14],        r/w,        0x0 */
            uint32_t cr_pds_force_usb_mem_stby : 1;  /* [   15],        r/w,        0x0 */
            uint32_t cr_pds_force_np_gate_clk  : 1;  /* [   16],        r/w,        0x0 */
            uint32_t reserved_17               : 1;  /* [   17],       rsvd,        0x0 */
            uint32_t cr_pds_force_wb_gate_clk  : 1;  /* [   18],        r/w,        0x0 */
            uint32_t cr_pds_force_usb_gate_clk : 1;  /* [   19],        r/w,        0x0 */
            uint32_t reserved_20_31            : 12; /* [31:20],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } PDS_CTL2;

    /* 0x14 : PDS_CTL3 */
    union {
        struct {
            uint32_t reserved_0                 : 1;  /* [    0],       rsvd,        0x0 */
            uint32_t cr_pds_force_misc_pwr_off  : 1;  /* [    1],        r/w,        0x0 */
            uint32_t reserved_2_3               : 2;  /* [ 3: 2],       rsvd,        0x0 */
            uint32_t cr_pds_force_misc_iso_en   : 1;  /* [    4],        r/w,        0x0 */
            uint32_t reserved_5_6               : 2;  /* [ 6: 5],       rsvd,        0x0 */
            uint32_t cr_pds_force_misc_pds_rst  : 1;  /* [    7],        r/w,        0x0 */
            uint32_t reserved_8_9               : 2;  /* [ 9: 8],       rsvd,        0x0 */
            uint32_t cr_pds_force_misc_mem_stby : 1;  /* [   10],        r/w,        0x0 */
            uint32_t reserved_11_12             : 2;  /* [12:11],       rsvd,        0x0 */
            uint32_t cr_pds_force_misc_gate_clk : 1;  /* [   13],        r/w,        0x0 */
            uint32_t reserved_14_23             : 10; /* [23:14],       rsvd,        0x0 */
            uint32_t cr_pds_np_iso_en           : 1;  /* [   24],        r/w,        0x1 */
            uint32_t reserved_25_26             : 2;  /* [26:25],       rsvd,        0x0 */
            uint32_t cr_pds_wb_iso_en           : 1;  /* [   27],        r/w,        0x1 */
            uint32_t reserved_28                : 1;  /* [   28],       rsvd,        0x0 */
            uint32_t cr_pds_usb_iso_en          : 1;  /* [   29],        r/w,        0x1 */
            uint32_t cr_pds_misc_iso_en         : 1;  /* [   30],        r/w,        0x1 */
            uint32_t reserved_31                : 1;  /* [   31],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } PDS_CTL3;

    /* 0x18 : PDS_CTL4 */
    union {
        struct {
            uint32_t cr_pds_np_pwr_off    : 1; /* [    0],        r/w,        0x1 */
            uint32_t cr_pds_np_reset      : 1; /* [    1],        r/w,        0x1 */
            uint32_t cr_pds_np_mem_stby   : 1; /* [    2],        r/w,        0x1 */
            uint32_t cr_pds_np_gate_clk   : 1; /* [    3],        r/w,        0x1 */
            uint32_t reserved_4_11        : 8; /* [11: 4],       rsvd,        0x0 */
            uint32_t cr_pds_wb_pwr_off    : 1; /* [   12],        r/w,        0x1 */
            uint32_t cr_pds_wb_reset      : 1; /* [   13],        r/w,        0x1 */
            uint32_t cr_pds_wb_mem_stby   : 1; /* [   14],        r/w,        0x1 */
            uint32_t cr_pds_wb_gate_clk   : 1; /* [   15],        r/w,        0x1 */
            uint32_t reserved_16_19       : 4; /* [19:16],       rsvd,        0x0 */
            uint32_t cr_pds_usb_pwr_off   : 1; /* [   20],        r/w,        0x1 */
            uint32_t cr_pds_usb_reset     : 1; /* [   21],        r/w,        0x1 */
            uint32_t cr_pds_usb_mem_stby  : 1; /* [   22],        r/w,        0x1 */
            uint32_t cr_pds_usb_gate_clk  : 1; /* [   23],        r/w,        0x1 */
            uint32_t cr_pds_misc_pwr_off  : 1; /* [   24],        r/w,        0x1 */
            uint32_t cr_pds_misc_reset    : 1; /* [   25],        r/w,        0x1 */
            uint32_t cr_pds_misc_mem_stby : 1; /* [   26],        r/w,        0x1 */
            uint32_t cr_pds_misc_gate_clk : 1; /* [   27],        r/w,        0x1 */
            uint32_t reserved_28_31       : 4; /* [31:28],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } PDS_CTL4;

    /* 0x1C : pds_stat */
    union {
        struct {
            uint32_t ro_pds_state        : 5;  /* [ 4: 0],          r,        0x0 */
            uint32_t reserved_5_7        : 3;  /* [ 7: 5],       rsvd,        0x0 */
            uint32_t ro_pds_rf_state     : 5;  /* [12: 8],          r,        0x0 */
            uint32_t reserved_13_23      : 11; /* [23:13],       rsvd,        0x0 */
            uint32_t pds_reset_event     : 3;  /* [26:24],          r,        0x0 */
            uint32_t reserved_27_30      : 4;  /* [30:27],       rsvd,        0x0 */
            uint32_t pds_clr_reset_event : 1;  /* [   31],        w1c,        0x0 */
        } BF;
        uint32_t WORD;
    } pds_stat;

    /* 0x20 : pds_ram1 */
    union {
        struct {
            uint32_t reserved_0_7             : 8; /* [ 7: 0],       rsvd,        0x0 */
            uint32_t cr_pds_ram_clk_cnt       : 6; /* [13: 8],        r/w,        0x8 */
            uint32_t reserved_14_15           : 2; /* [15:14],       rsvd,        0x0 */
            uint32_t cr_pds_ram_clk2_cnt      : 6; /* [21:16],        r/w,       0x18 */
            uint32_t reserved_22_23           : 2; /* [23:22],       rsvd,        0x0 */
            uint32_t cr_pds_ctrl_np_ram_clk   : 1; /* [   24],        r/w,        0x0 */
            uint32_t reserved_25              : 1; /* [   25],       rsvd,        0x0 */
            uint32_t cr_pds_ctrl_wb_ram_clk   : 1; /* [   26],        r/w,        0x0 */
            uint32_t cr_pds_ctrl_usb_ram_clk  : 1; /* [   27],        r/w,        0x0 */
            uint32_t cr_pds_ctrl_misc_ram_clk : 1; /* [   28],        r/w,        0x0 */
            uint32_t reserved_29              : 1; /* [   29],       rsvd,        0x0 */
            uint32_t cr_pds_ctrl_ram_clk2     : 1; /* [   30],        r/w,        0x0 */
            uint32_t cr_pds_ctrl_ram_clk      : 1; /* [   31],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } pds_ram1;

    /* 0x24 : PDS_CTL5 */
    union {
        struct {
            uint32_t cr_np_wfi_mask      : 1;  /* [    0],        r/w,        0x0 */
            uint32_t cr_pds_pad_od_en    : 1;  /* [    1],        r/w,        0x0 */
            uint32_t reserved_2_7        : 6;  /* [ 7: 2],       rsvd,        0x0 */
            uint32_t cr_pds_ctrl_usb33   : 1;  /* [    8],        r/w,        0x0 */
            uint32_t cr_pds_pd_ldo18io   : 1;  /* [    9],        r/w,        0x0 */
            uint32_t reserved_10_15      : 6;  /* [15:10],       rsvd,        0x0 */
            uint32_t cr_pds_gpio_keep_en : 3;  /* [18:16],        r/w,        0x7 */
            uint32_t reserved_19_31      : 13; /* [31:19],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } PDS_CTL5;

    /* 0x28 : PDS_RAM2 */
    union {
        struct {
            uint32_t cr_wram_slp    : 10; /* [ 9: 0],        r/w,        0x0 */
            uint32_t cr_wram_ret    : 10; /* [19:10],        r/w,        0x0 */
            uint32_t reserved_20_31 : 12; /* [31:20],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } PDS_RAM2;

    /* 0x2c  reserved */
    uint8_t RESERVED0x2c[4];

    /* 0x30 : pds_gpio_i_set */
    union {
        struct {
            uint32_t cr_pds_gpio_ie_set : 2;  /* [ 1: 0],        r/w,        0x0 */
            uint32_t reserved_2         : 1;  /* [    2],       rsvd,        0x0 */
            uint32_t cr_pds_gpio_pd_set : 2;  /* [ 4: 3],        r/w,        0x0 */
            uint32_t reserved_5         : 1;  /* [    5],       rsvd,        0x0 */
            uint32_t cr_pds_gpio_pu_set : 2;  /* [ 7: 6],        r/w,        0x0 */
            uint32_t reserved_8_31      : 24; /* [31: 8],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } pds_gpio_i_set;

    /* 0x34 : pds_gpio_pd_set */
    union {
        struct {
            uint32_t cr_pds_gpio_set_int_mask : 31; /* [30: 0],        r/w, 0x7fffffff */
            uint32_t reserved_31              : 1;  /* [   31],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } pds_gpio_pd_set;

    /* 0x38  reserved */
    uint8_t RESERVED0x38[8];

    /* 0x40 : pds_gpio_int */
    union {
        struct {
            uint32_t reserved_0_1           : 2; /* [ 1: 0],       rsvd,        0x0 */
            uint32_t pds_gpio_set1_int_clr  : 1; /* [    2],        r/w,        0x0 */
            uint32_t reserved_3             : 1; /* [    3],       rsvd,        0x0 */
            uint32_t pds_gpio_set1_int_mode : 4; /* [ 7: 4],        r/w,        0x0 */
            uint32_t reserved_8_9           : 2; /* [ 9: 8],       rsvd,        0x0 */
            uint32_t pds_gpio_set2_int_clr  : 1; /* [   10],        r/w,        0x0 */
            uint32_t reserved_11            : 1; /* [   11],       rsvd,        0x0 */
            uint32_t pds_gpio_set2_int_mode : 4; /* [15:12],        r/w,        0x0 */
            uint32_t reserved_16_17         : 2; /* [17:16],       rsvd,        0x0 */
            uint32_t pds_gpio_set3_int_clr  : 1; /* [   18],        r/w,        0x0 */
            uint32_t reserved_19            : 1; /* [   19],       rsvd,        0x0 */
            uint32_t pds_gpio_set3_int_mode : 4; /* [23:20],        r/w,        0x0 */
            uint32_t reserved_24_25         : 2; /* [25:24],       rsvd,        0x0 */
            uint32_t pds_gpio_set4_int_clr  : 1; /* [   26],        r/w,        0x0 */
            uint32_t reserved_27            : 1; /* [   27],       rsvd,        0x0 */
            uint32_t pds_gpio_set4_int_mode : 4; /* [31:28],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } pds_gpio_int;

    /* 0x44 : pds_gpio_stat */
    union {
        struct {
            uint32_t pds_gpio_int_stat : 31; /* [30: 0],          r,        0x0 */
            uint32_t reserved_31       : 1;  /* [   31],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } pds_gpio_stat;

    /* 0x48 : PDS_RAM3 */
    union {
        struct {
            uint32_t cr_ocram_ret   : 20; /* [19: 0],        r/w,        0x0 */
            uint32_t reserved_20_31 : 12; /* [31:20],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } PDS_RAM3;

    /* 0x4C : PDS_RAM4 */
    union {
        struct {
            uint32_t cr_ocram_slp   : 20; /* [19: 0],        r/w,        0x0 */
            uint32_t reserved_20_31 : 12; /* [31:20],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } PDS_RAM4;

    /* 0x50  reserved */
    uint8_t RESERVED0x50[196];

    /* 0x114 : cpu_core_cfg1 */
    union {
        struct {
            uint32_t reserved_0_3    : 4;  /* [ 3: 0],       rsvd,        0x0 */
            uint32_t reg_pll_sel     : 2;  /* [ 5: 4],        r/w,        0x3 */
            uint32_t reserved_6_7    : 2;  /* [ 7: 6],       rsvd,        0x0 */
            uint32_t reg_mcu1_clk_en : 1;  /* [    8],        r/w,        0x1 */
            uint32_t reserved_9_31   : 23; /* [31: 9],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } cpu_core_cfg1;

    /* 0x118  reserved */
    uint8_t RESERVED0x118[48];

    /* 0x148 : cpu_core_cfg14 */
    union {
        struct {
            uint32_t e906_rst_addr : 32; /* [31: 0],        r/w, 0x90000000 */
        } BF;
        uint32_t WORD;
    } cpu_core_cfg14;

    /* 0x14c  reserved */
    uint8_t RESERVED0x14c[436];

    /* 0x300 : rc32m_ctrl0 */
    union {
        struct {
            uint32_t rc32m_cal_done        : 1; /* [    0],          r,        0x0 */
            uint32_t rc32m_rdy             : 1; /* [    1],          r,        0x0 */
            uint32_t rc32m_cal_inprogress  : 1; /* [    2],          r,        0x0 */
            uint32_t rc32m_cal_div         : 2; /* [ 4: 3],        r/w,        0x3 */
            uint32_t rc32m_cal_precharge   : 1; /* [    5],          r,        0x0 */
            uint32_t rc32m_dig_code_fr_cal : 8; /* [13: 6],          r,        0x0 */
            uint32_t reserved_14_16        : 3; /* [16:14],       rsvd,        0x0 */
            uint32_t rc32m_allow_cal       : 1; /* [   17],        r/w,        0x0 */
            uint32_t rc32m_refclk_half     : 1; /* [   18],        r/w,        0x0 */
            uint32_t rc32m_ext_code_en     : 1; /* [   19],        r/w,        0x1 */
            uint32_t rc32m_cal_en          : 1; /* [   20],        r/w,        0x0 */
            uint32_t rc32m_pd              : 1; /* [   21],        r/w,        0x0 */
            uint32_t rc32m_code_fr_ext     : 8; /* [29:22],        r/w,       0x60 */
            uint32_t reserved_30_31        : 2; /* [31:30],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } rc32m_ctrl0;

    /* 0x304 : rc32m_ctrl1 */
    union {
        struct {
            uint32_t rc32m_test_en      : 1;  /* [    0],        r/w,        0x0 */
            uint32_t rc32m_soft_rst     : 1;  /* [    1],        r/w,        0x0 */
            uint32_t rc32m_clk_soft_rst : 1;  /* [    2],        r/w,        0x0 */
            uint32_t rc32m_clk_inv      : 1;  /* [    3],        r/w,        0x0 */
            uint32_t rc32m_clk_force_on : 1;  /* [    4],        r/w,        0x0 */
            uint32_t reserved_5_23      : 19; /* [23: 5],       rsvd,        0x0 */
            uint32_t rc32m_reserved     : 8;  /* [31:24],        r/w,        0xf */
        } BF;
        uint32_t WORD;
    } rc32m_ctrl1;

    /* 0x308 : rc32m_ctrl2 */
    union {
        struct {
            uint32_t reserved_0_21      : 22; /* [21: 0],       rsvd,        0x0 */
            uint32_t rc32m_code_fr_ext2 : 8;  /* [29:22],        r/w,       0x60 */
            uint32_t reserved_30        : 1;  /* [   30],       rsvd,        0x0 */
            uint32_t rc32m_ext_code_sel : 1;  /* [   31],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } rc32m_ctrl2;

    /* 0x30c  reserved */
    uint8_t RESERVED0x30c[244];

    /* 0x400 : pu_rst_clkpll */
    union {
        struct {
            uint32_t reserved_0_8           : 9;  /* [ 8: 0],       rsvd,        0x0 */
            uint32_t cr_pds_pu_clkpll_sfreg : 1;  /* [    9],        r/w,        0x0 */
            uint32_t cr_pds_pu_clkpll       : 1;  /* [   10],        r/w,        0x0 */
            uint32_t reserved_11_31         : 21; /* [31:11],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } pu_rst_clkpll;

    /* 0x404  reserved */
    uint8_t RESERVED0x404[252];

    /* 0x500 : usb_ctl */
    union {
        struct {
            uint32_t reg_usb_sw_rst_n   : 1;  /* [    0],        r/w,        0x1 */
            uint32_t reg_usb_ext_susp_n : 1;  /* [    1],        r/w,        0x0 */
            uint32_t reg_usb_wakeup     : 1;  /* [    2],        r/w,        0x0 */
            uint32_t reg_usb_l1_wakeup  : 1;  /* [    3],        r/w,        0x0 */
            uint32_t reg_usb_drvbus_pol : 1;  /* [    4],        r/w,        0x0 */
            uint32_t reg_usb_iddig      : 1;  /* [    5],        r/w,        0x1 */
            uint32_t reserved_6_31      : 26; /* [31: 6],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } usb_ctl;

    /* 0x504 : usb_phy_ctrl */
    union {
        struct {
            uint32_t reg_usb_phy_ponrst    : 1;  /* [    0],        r/w,        0x0 */
            uint32_t reg_usb_phy_oscouten  : 1;  /* [    1],        r/w,        0x0 */
            uint32_t reg_usb_phy_xtlsel    : 2;  /* [ 3: 2],        r/w,        0x0 */
            uint32_t reg_usb_phy_outclksel : 1;  /* [    4],        r/w,        0x0 */
            uint32_t reg_usb_phy_pllaliv   : 1;  /* [    5],        r/w,        0x0 */
            uint32_t reg_pu_usb20_psw      : 1;  /* [    6],        r/w,        0x0 */
            uint32_t reserved_7_31         : 25; /* [31: 7],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } usb_phy_ctrl;
};

typedef volatile struct pds_reg pds_reg_t;

#endif /* __PDS_REG_H__ */
